{"id":"https://openalex.org/W1509538169","doi":"https://doi.org/10.1007/3-540-46117-5_26","title":"Rapid and Reliable Routability Estimation for FPGAs","display_name":"Rapid and Reliable Routability Estimation for FPGAs","publication_year":2002,"publication_date":"2002-01-01","ids":{"openalex":"https://openalex.org/W1509538169","doi":"https://doi.org/10.1007/3-540-46117-5_26","mag":"1509538169"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-46117-5_26","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-46117-5_26","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112222457","display_name":"Parivallal Kannan","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Parivallal Kannan","raw_affiliation_strings":["Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, PO Box 830688, 75083, Richardson, TX, USA","University of Texas at Dallas"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, PO Box 830688, 75083, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"University of Texas at Dallas","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053893441","display_name":"Shankar Balachandran","orcid":"https://orcid.org/0000-0002-5893-1604"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shankar Balachandran","raw_affiliation_strings":["Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, PO Box 830688, 75083, Richardson, TX, USA","University of Texas at Dallas"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, PO Box 830688, 75083, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"University of Texas at Dallas","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069692759","display_name":"Dinesh Bhatia","orcid":"https://orcid.org/0000-0002-5019-7417"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Bhatia","raw_affiliation_strings":["Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, PO Box 830688, 75083, Richardson, TX, USA","University of Texas at Dallas"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, PO Box 830688, 75083, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"University of Texas at Dallas","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112222457"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.13523248,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"242","last_page":"252"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.78886479139328},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7708563208580017},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6923090815544128},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6868101954460144},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.6029365658760071},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5630037784576416},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5533867478370667},{"id":"https://openalex.org/keywords/estimation","display_name":"Estimation","score":0.4804077446460724},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.463522732257843},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.44852086901664734},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3573850691318512},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3533325493335724},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0827031135559082}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.78886479139328},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7708563208580017},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6923090815544128},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6868101954460144},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.6029365658760071},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5630037784576416},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5533867478370667},{"id":"https://openalex.org/C96250715","wikidata":"https://www.wikidata.org/wiki/Q965330","display_name":"Estimation","level":2,"score":0.4804077446460724},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.463522732257843},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.44852086901664734},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3573850691318512},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3533325493335724},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0827031135559082},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-46117-5_26","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-46117-5_26","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1544514719","https://openalex.org/W1556480701","https://openalex.org/W1568029617","https://openalex.org/W1585249527","https://openalex.org/W1806243670","https://openalex.org/W1991530123","https://openalex.org/W1995004404","https://openalex.org/W2063781085","https://openalex.org/W2083554492","https://openalex.org/W2110265185","https://openalex.org/W2112547226","https://openalex.org/W2139637699","https://openalex.org/W2147657819","https://openalex.org/W2170632296","https://openalex.org/W2178250393","https://openalex.org/W2178873339","https://openalex.org/W4254598290"],"related_works":["https://openalex.org/W4231704780","https://openalex.org/W2083794993","https://openalex.org/W352609212","https://openalex.org/W2122026593","https://openalex.org/W1511772879","https://openalex.org/W4379115841","https://openalex.org/W4200340037","https://openalex.org/W608917066","https://openalex.org/W4283652261","https://openalex.org/W585424826"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
