{"id":"https://openalex.org/W1599997933","doi":"https://doi.org/10.1007/3-540-45373-3_20","title":"VLSI Implementation of a Low-Power High-Speed Self-Timed Adder","display_name":"VLSI Implementation of a Low-Power High-Speed Self-Timed Adder","publication_year":2000,"publication_date":"2000-01-01","ids":{"openalex":"https://openalex.org/W1599997933","doi":"https://doi.org/10.1007/3-540-45373-3_20","mag":"1599997933"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-45373-3_20","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-45373-3_20","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003003043","display_name":"Pasquale Corsonello","orcid":"https://orcid.org/0000-0002-9528-1110"},"institutions":[{"id":"https://openalex.org/I59725666","display_name":"University of Reggio Calabria","ror":"https://ror.org/041sz8d87","country_code":"IT","type":"education","lineage":["https://openalex.org/I59725666"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Pasquale Corsonello","raw_affiliation_strings":["Department of Electronic Engineering and Applied Mathematics, University of Reggio Calabria, Loc. Vito de Feo, 88100, Reggio Calabria, ITALY"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering and Applied Mathematics, University of Reggio Calabria, Loc. Vito de Feo, 88100, Reggio Calabria, ITALY","institution_ids":["https://openalex.org/I59725666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074662921","display_name":"Stefania Perri","orcid":"https://orcid.org/0000-0003-1363-9201"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Stefania Perri","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, 87036, Rende (CS), ITALY"],"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, 87036, Rende (CS), ITALY","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032249162","display_name":"G. Cocorullo","orcid":"https://orcid.org/0000-0001-9133-0774"},"institutions":[{"id":"https://openalex.org/I4210155236","display_name":"National Research Council","ror":"https://ror.org/04zaypm56","country_code":"IT","type":"funder","lineage":["https://openalex.org/I4210155236"]},{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Cocorullo","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, 87036, Rende (CS), ITALY","IRECE-National Council of Research, Via Diocleziano, 328, 80125, Napoli, ITALY"],"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, 87036, Rende (CS), ITALY","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"IRECE-National Council of Research, Via Diocleziano, 328, 80125, Napoli, ITALY","institution_ids":["https://openalex.org/I4210155236"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5003003043"],"corresponding_institution_ids":["https://openalex.org/I59725666"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":6.3088,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.95814688,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"195","last_page":"204"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7561371326446533},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6816249489784241},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5959603786468506},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5521565079689026},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5239130258560181},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5125610828399658},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48780062794685364},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4419375956058502},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42779189348220825},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4147009253501892},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30173203349113464},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25427600741386414},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.22115793824195862},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19207081198692322},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16881626844406128},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.13154137134552002}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7561371326446533},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6816249489784241},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5959603786468506},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5521565079689026},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5239130258560181},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5125610828399658},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48780062794685364},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4419375956058502},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42779189348220825},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4147009253501892},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30173203349113464},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25427600741386414},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.22115793824195862},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19207081198692322},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16881626844406128},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.13154137134552002},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-45373-3_20","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-45373-3_20","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2061539835","https://openalex.org/W2114489915","https://openalex.org/W2121914493","https://openalex.org/W2142118268","https://openalex.org/W2150623514","https://openalex.org/W2153257335"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W2016936938","https://openalex.org/W2526300902","https://openalex.org/W2125567818","https://openalex.org/W1553855433","https://openalex.org/W2170504327","https://openalex.org/W1827076955","https://openalex.org/W2066280488","https://openalex.org/W2121963733","https://openalex.org/W2542337934"],"abstract_inverted_index":null,"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}