{"id":"https://openalex.org/W2111698824","doi":"https://doi.org/10.1007/3-540-44798-9_9","title":"Formally-Based Design Evaluation","display_name":"Formally-Based Design Evaluation","publication_year":2001,"publication_date":"2001-01-01","ids":{"openalex":"https://openalex.org/W2111698824","doi":"https://doi.org/10.1007/3-540-44798-9_9","mag":"2111698824"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-44798-9_9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-44798-9_9","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011202875","display_name":"Kenneth J. Turner","orcid":null},"institutions":[{"id":"https://openalex.org/I12093191","display_name":"University of Stirling","ror":"https://ror.org/045wgfr59","country_code":"GB","type":"education","lineage":["https://openalex.org/I12093191"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Kenneth J. Turner","raw_affiliation_strings":["Computing Science and Mathematics, University of Stirling, Stirling, FK9 4PU, Scotland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computing Science and Mathematics, University of Stirling, Stirling, FK9 4PU, Scotland","institution_ids":["https://openalex.org/I12093191"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102061444","display_name":"Ji He","orcid":"https://orcid.org/0000-0001-8160-9173"},"institutions":[{"id":"https://openalex.org/I12093191","display_name":"University of Stirling","ror":"https://ror.org/045wgfr59","country_code":"GB","type":"education","lineage":["https://openalex.org/I12093191"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Ji He","raw_affiliation_strings":["Computing Science and Mathematics, University of Stirling, Stirling, FK9 4PU, Scotland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computing Science and Mathematics, University of Stirling, Stirling, FK9 4PU, Scotland","institution_ids":["https://openalex.org/I12093191"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I12093191"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"104","last_page":"109"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8706957697868347},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.7223477959632874},{"id":"https://openalex.org/keywords/specification-language","display_name":"Specification language","score":0.6807150840759277},{"id":"https://openalex.org/keywords/language-of-temporal-ordering-specification","display_name":"Language Of Temporal Ordering Specification","score":0.665924608707428},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6584288477897644},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.6037402153015137},{"id":"https://openalex.org/keywords/conformance-testing","display_name":"Conformance testing","score":0.5363624691963196},{"id":"https://openalex.org/keywords/programming-language-specification","display_name":"Programming language specification","score":0.47553396224975586},{"id":"https://openalex.org/keywords/logic-analyzer","display_name":"Logic analyzer","score":0.45826277136802673},{"id":"https://openalex.org/keywords/temporal-logic","display_name":"Temporal logic","score":0.45627182722091675},{"id":"https://openalex.org/keywords/system-requirements-specification","display_name":"System requirements specification","score":0.4312905967235565},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4219190776348114},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4115893542766571},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3263259530067444},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10699334740638733},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.08926460146903992}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8706957697868347},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.7223477959632874},{"id":"https://openalex.org/C201677973","wikidata":"https://www.wikidata.org/wiki/Q1209840","display_name":"Specification language","level":2,"score":0.6807150840759277},{"id":"https://openalex.org/C90069079","wikidata":"https://www.wikidata.org/wiki/Q1805432","display_name":"Language Of Temporal Ordering Specification","level":3,"score":0.665924608707428},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6584288477897644},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.6037402153015137},{"id":"https://openalex.org/C76844732","wikidata":"https://www.wikidata.org/wiki/Q4072285","display_name":"Conformance testing","level":3,"score":0.5363624691963196},{"id":"https://openalex.org/C15077461","wikidata":"https://www.wikidata.org/wiki/Q7248507","display_name":"Programming language specification","level":5,"score":0.47553396224975586},{"id":"https://openalex.org/C188434589","wikidata":"https://www.wikidata.org/wiki/Q1478762","display_name":"Logic analyzer","level":3,"score":0.45826277136802673},{"id":"https://openalex.org/C25016198","wikidata":"https://www.wikidata.org/wiki/Q781833","display_name":"Temporal logic","level":2,"score":0.45627182722091675},{"id":"https://openalex.org/C84651959","wikidata":"https://www.wikidata.org/wiki/Q17052506","display_name":"System requirements specification","level":2,"score":0.4312905967235565},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4219190776348114},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4115893542766571},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3263259530067444},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10699334740638733},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.08926460146903992},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C50033165","wikidata":"https://www.wikidata.org/wiki/Q15712089","display_name":"Inductive programming","level":3,"score":0.0},{"id":"https://openalex.org/C119263510","wikidata":"https://www.wikidata.org/wiki/Q7248501","display_name":"Programming domain","level":4,"score":0.0},{"id":"https://openalex.org/C188087704","wikidata":"https://www.wikidata.org/wiki/Q369577","display_name":"Standardization","level":2,"score":0.0},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.0},{"id":"https://openalex.org/C158007255","wikidata":"https://www.wikidata.org/wiki/Q1055222","display_name":"Spectrum analyzer","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/3-540-44798-9_9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-44798-9_9","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.64.9310","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.64.9310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.stir.ac.uk/~kjt/research/pdf/form-des.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.7.2897","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.2897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ftp://ftp.cs.stir.ac.uk/pub/staff/kjt/research/pubs/form-des.ps.gz","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1491037212","https://openalex.org/W1493750737","https://openalex.org/W1567947631","https://openalex.org/W1601260964","https://openalex.org/W1965674893","https://openalex.org/W2009653580","https://openalex.org/W2112640524","https://openalex.org/W2126848377","https://openalex.org/W2131600432","https://openalex.org/W2161294792","https://openalex.org/W2167352300","https://openalex.org/W2674269739","https://openalex.org/W4285719527","https://openalex.org/W6605910214"],"related_works":["https://openalex.org/W794225219","https://openalex.org/W2047524021","https://openalex.org/W1975565207","https://openalex.org/W2313419847","https://openalex.org/W9205283","https://openalex.org/W2117824779","https://openalex.org/W4245140145","https://openalex.org/W2112029416","https://openalex.org/W2558572842","https://openalex.org/W1970003032"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
