{"id":"https://openalex.org/W1570833211","doi":"https://doi.org/10.1007/3-540-44687-7_50","title":"Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification","display_name":"Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification","publication_year":2001,"publication_date":"2001-01-01","ids":{"openalex":"https://openalex.org/W1570833211","doi":"https://doi.org/10.1007/3-540-44687-7_50","mag":"1570833211"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-44687-7_50","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-44687-7_50","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005959008","display_name":"Timothy Wheeler","orcid":null},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Timothy Wheeler","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089573935","display_name":"Paul Graham","orcid":"https://orcid.org/0000-0002-3745-0940"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Graham","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083691929","display_name":"Brent Nelson","orcid":"https://orcid.org/0000-0002-2436-5894"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brent Nelson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018034033","display_name":"Brad Hutchings","orcid":"https://orcid.org/0000-0002-2991-0230"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brad Hutchings","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5005959008"],"corresponding_institution_ids":["https://openalex.org/I100005738"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.9578,"has_fulltext":false,"cited_by_count":59,"citation_normalized_percentile":{"value":0.73630573,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"483","last_page":"492"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.9070796370506287},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8489772081375122},{"id":"https://openalex.org/keywords/controllability","display_name":"Controllability","score":0.8405733704566956},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.8271110653877258},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7891883254051208},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6806748509407043},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5857045650482178},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5314786434173584},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5021307468414307},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4107731282711029},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32935529947280884},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24330726265907288},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1977689564228058},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.09514680504798889},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08988833427429199},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07172787189483643}],"concepts":[{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.9070796370506287},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8489772081375122},{"id":"https://openalex.org/C48209547","wikidata":"https://www.wikidata.org/wiki/Q1331104","display_name":"Controllability","level":2,"score":0.8405733704566956},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.8271110653877258},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7891883254051208},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6806748509407043},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5857045650482178},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5314786434173584},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5021307468414307},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4107731282711029},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32935529947280884},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24330726265907288},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1977689564228058},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.09514680504798889},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08988833427429199},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07172787189483643},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-44687-7_50","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-44687-7_50","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1603444000","https://openalex.org/W1830708738","https://openalex.org/W2034476614","https://openalex.org/W2107725243","https://openalex.org/W2130331200","https://openalex.org/W2156253418","https://openalex.org/W2158583421","https://openalex.org/W2936804578","https://openalex.org/W4235641964","https://openalex.org/W4241851591","https://openalex.org/W4302860535"],"related_works":["https://openalex.org/W1986570998","https://openalex.org/W2332386680","https://openalex.org/W1983142522","https://openalex.org/W2782529250","https://openalex.org/W2037921533","https://openalex.org/W2508171592","https://openalex.org/W2801563517","https://openalex.org/W2130864543","https://openalex.org/W2068126039","https://openalex.org/W2041749520"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":9}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}