{"id":"https://openalex.org/W1535100460","doi":"https://doi.org/10.1007/11556930_65","title":"Power-Clock Gating in Adiabatic Logic Circuits","display_name":"Power-Clock Gating in Adiabatic Logic Circuits","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W1535100460","doi":"https://doi.org/10.1007/11556930_65","mag":"1535100460"},"language":"en","primary_location":{"id":"doi:10.1007/11556930_65","is_oa":false,"landing_page_url":"https://doi.org/10.1007/11556930_65","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040915824","display_name":"Philip Teichmann","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Philip Teichmann","raw_affiliation_strings":["Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108290989","display_name":"J\u00fcrgen Fischer","orcid":"https://orcid.org/0000-0002-6789-6062"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J\u00fcrgen Fischer","raw_affiliation_strings":["Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111472507","display_name":"Stephan Henzler","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stephan Henzler","raw_affiliation_strings":["Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007303066","display_name":"E. Amirante","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ettore Amirante","raw_affiliation_strings":["Now with Infineon Technologies, Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Now with Infineon Technologies, Munich","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034576088","display_name":"D. Schmitt\u2010Landsiedel","orcid":"https://orcid.org/0000-0002-4817-5139"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Doris Schmitt-Landsiedel","raw_affiliation_strings":["Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Technical Electronics, Technical University Munich, Theresienstrasse 90, D-80290, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5040915824"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":3.7812,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.93098467,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"638","last_page":"646"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.8778941631317139},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.8748283982276917},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.6724287271499634},{"id":"https://openalex.org/keywords/adiabatic-process","display_name":"Adiabatic process","score":0.5451405048370361},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5139009952545166},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5007543563842773},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.471441388130188},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4650823473930359},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.44085219502449036},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.43190425634384155},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4247044026851654},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.39771634340286255},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39190903306007385},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3915315866470337},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.37360885739326477},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.32394564151763916},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.323464035987854},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.30442604422569275},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2279186248779297},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.1976332664489746},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.18810978531837463},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1315600574016571}],"concepts":[{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.8778941631317139},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8748283982276917},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.6724287271499634},{"id":"https://openalex.org/C109663097","wikidata":"https://www.wikidata.org/wiki/Q182453","display_name":"Adiabatic process","level":2,"score":0.5451405048370361},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5139009952545166},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5007543563842773},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.471441388130188},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4650823473930359},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.44085219502449036},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.43190425634384155},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4247044026851654},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.39771634340286255},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39190903306007385},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3915315866470337},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.37360885739326477},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.32394564151763916},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.323464035987854},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.30442604422569275},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2279186248779297},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.1976332664489746},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.18810978531837463},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1315600574016571},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/11556930_65","is_oa":false,"landing_page_url":"https://doi.org/10.1007/11556930_65","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1556675666","https://openalex.org/W1989315484","https://openalex.org/W2000700787","https://openalex.org/W2085952730","https://openalex.org/W2103684670","https://openalex.org/W2122984966","https://openalex.org/W2145071646","https://openalex.org/W3198221827"],"related_works":["https://openalex.org/W2100899581","https://openalex.org/W2548567058","https://openalex.org/W2158114058","https://openalex.org/W2113758237","https://openalex.org/W2898743978","https://openalex.org/W2557143395","https://openalex.org/W2188626039","https://openalex.org/W1535100460","https://openalex.org/W2090602390","https://openalex.org/W1501225614"],"abstract_inverted_index":null,"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}