{"id":"https://openalex.org/W1921869937","doi":"https://doi.org/10.1007/0-387-48550-3","title":"Routing Congestion in VLSI Circuits: Estimation and Optimization","display_name":"Routing Congestion in VLSI Circuits: Estimation and Optimization","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W1921869937","doi":"https://doi.org/10.1007/0-387-48550-3","mag":"1921869937"},"language":"en","primary_location":{"id":"doi:10.1007/0-387-48550-3","is_oa":false,"landing_page_url":"https://doi.org/10.1007/0-387-48550-3","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Series on Integrated Circuits and Systems","raw_type":"book"},"type":"book","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111649792","display_name":"Prashant Saxena","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saxena, Prashant","raw_affiliation_strings":["Synopsys, Inc., Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Hillsboro, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029632511","display_name":"Rupesh S. Shelar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shelar, Rupesh S.","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sapatnekar, Sachin S.","raw_affiliation_strings":["University of Minnesota, Minneapolis, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, Minneapolis, USA","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0701,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.87720444,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7291065454483032},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5757561922073364},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5555461645126343},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4788634479045868},{"id":"https://openalex.org/keywords/estimation","display_name":"Estimation","score":0.4500347971916199},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3640793263912201},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.26801353693008423},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22001692652702332},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1899891197681427},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16979685425758362},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.0803118646144867}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7291065454483032},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5757561922073364},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5555461645126343},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4788634479045868},{"id":"https://openalex.org/C96250715","wikidata":"https://www.wikidata.org/wiki/Q965330","display_name":"Estimation","level":2,"score":0.4500347971916199},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3640793263912201},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.26801353693008423},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22001692652702332},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1899891197681427},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16979685425758362},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0803118646144867}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/0-387-48550-3","is_oa":false,"landing_page_url":"https://doi.org/10.1007/0-387-48550-3","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Series on Integrated Circuits and Systems","raw_type":"book"},{"id":"pmh:oai:dial.uclouvain.be:ebook:8002","is_oa":false,"landing_page_url":"http://hdl.handle.net/2078/ebook:8002","pdf_url":null,"source":{"id":"https://openalex.org/S4306401902","display_name":"Digital Access to Libraries (Universit\u00e9 catholique de Louvain (UCL), l'Universit\u00e9 de Namur (UNamur) and the Universit\u00e9 Saint-Louis (USL-B))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I95674353","host_organization_name":"UCLouvain","host_organization_lineage":["https://openalex.org/I95674353"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W4254559750","https://openalex.org/W2050492524","https://openalex.org/W2998315020","https://openalex.org/W4205718258","https://openalex.org/W2059364457","https://openalex.org/W1989674257","https://openalex.org/W4241196849"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":4},{"year":2012,"cited_by_count":4}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}