{"id":"https://openalex.org/W2046985335","doi":"https://doi.org/10.1002/spe.4380180507","title":"Process\u2010graph analyser: A front\u2010end tool for VHDL behavioural synthesis","display_name":"Process\u2010graph analyser: A front\u2010end tool for VHDL behavioural synthesis","publication_year":1988,"publication_date":"1988-05-01","ids":{"openalex":"https://openalex.org/W2046985335","doi":"https://doi.org/10.1002/spe.4380180507","mag":"2046985335"},"language":"en","primary_location":{"id":"doi:10.1002/spe.4380180507","is_oa":false,"landing_page_url":"https://doi.org/10.1002/spe.4380180507","pdf_url":null,"source":{"id":"https://openalex.org/S122199241","display_name":"Software Practice and Experience","issn_l":"0038-0644","issn":["0038-0644","1097-024X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Software: Practice and Experience","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036946417","display_name":"J. Bhasker","orcid":null},"institutions":[{"id":"https://openalex.org/I82514191","display_name":"Honeywell (United States)","ror":"https://ror.org/02t71h845","country_code":"US","type":"company","lineage":["https://openalex.org/I82514191"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"J. Bhasker","raw_affiliation_strings":["Honeywell, Corporate Systems Development Division, 1000 Boone Avenue North, Golden Valley, MN 55427, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Honeywell, Corporate Systems Development Division, 1000 Boone Avenue North, Golden Valley, MN 55427, U.S.A","institution_ids":["https://openalex.org/I82514191"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5036946417"],"corresponding_institution_ids":["https://openalex.org/I82514191"],"apc_list":{"value":4220,"currency":"USD","value_usd":4220},"apc_paid":null,"fwci":1.6301,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.83923365,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":"5","first_page":"469","last_page":"483"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.849516749382019},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8203877210617065},{"id":"https://openalex.org/keywords/analyser","display_name":"Analyser","score":0.7678796052932739},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6566120386123657},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.6132214069366455},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5839996337890625},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5077368021011353},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5024216175079346},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4763662815093994},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4734109342098236},{"id":"https://openalex.org/keywords/preprocessor","display_name":"Preprocessor","score":0.4340442419052124},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40730348229408264},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3306480646133423},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3026573359966278},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.25822973251342773}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.849516749382019},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8203877210617065},{"id":"https://openalex.org/C26834552","wikidata":"https://www.wikidata.org/wiki/Q3275846","display_name":"Analyser","level":2,"score":0.7678796052932739},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6566120386123657},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.6132214069366455},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5839996337890625},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5077368021011353},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5024216175079346},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4763662815093994},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4734109342098236},{"id":"https://openalex.org/C34736171","wikidata":"https://www.wikidata.org/wiki/Q918333","display_name":"Preprocessor","level":2,"score":0.4340442419052124},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40730348229408264},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3306480646133423},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3026573359966278},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.25822973251342773},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C43617362","wikidata":"https://www.wikidata.org/wiki/Q170050","display_name":"Chromatography","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/spe.4380180507","is_oa":false,"landing_page_url":"https://doi.org/10.1002/spe.4380180507","pdf_url":null,"source":{"id":"https://openalex.org/S122199241","display_name":"Software Practice and Experience","issn_l":"0038-0644","issn":["0038-0644","1097-024X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Software: Practice and Experience","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W31150501","https://openalex.org/W1513250879","https://openalex.org/W1519924766","https://openalex.org/W1530971713","https://openalex.org/W1986207994","https://openalex.org/W2016558072","https://openalex.org/W2025554746","https://openalex.org/W2047615655","https://openalex.org/W2050464392","https://openalex.org/W2053013213","https://openalex.org/W2063747323","https://openalex.org/W2087376924","https://openalex.org/W2116098983","https://openalex.org/W2124153277","https://openalex.org/W2162436812","https://openalex.org/W3109454929","https://openalex.org/W4206153422","https://openalex.org/W4231345919","https://openalex.org/W4240999960"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2075214143","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582","https://openalex.org/W2077870657"],"abstract_inverted_index":{"Abstract":[0],"A":[1],"front\u2010end":[2],"of":[3,18,97,112],"an":[4,66],"electronic":[5],"CAD":[6],"synthesis":[7,12,47,60,115],"system":[8,13,21,48],"is":[9,65,109],"described.":[10],"The":[11,46,62,107],"accepts":[14],"a":[15,19,83,129],"behavioural":[16,132],"description":[17],"digital":[20],"design":[22,55],"written":[23],"in":[24],"VHSIC":[25],"Hardware":[26],"Description":[27],"Language":[28],"(VHDL)":[29],"and":[30,57,68],"produces":[31],"the":[32,36,43,58,95,98,113,135],"physical":[33],"hardware,":[34],"at":[35],"register":[37],"transfer":[38],"level,":[39],"needed":[40],"for":[41,77,87,102],"realizing":[42],"specified":[44],"behaviour.":[45],"comprises":[49],"three":[50],"major":[51],"subsystems:":[52],"process\u2010graph":[53,63],"analyser,":[54],"representation":[56,133],"MIMOLA":[59,118],"system.":[61],"analyser":[64],"optimization":[67,85],"parallelization":[69,96],"tool.":[70],"We":[71,90],"show":[72,122],"how":[73,123],"optimizing":[74],"techniques":[75,92],"used":[76],"compilers":[78],"are":[79],"adapted":[80],"to":[81,124],"perform":[82],"similar":[84],"function":[86],"hardware":[88],"synthesis.":[89],"present":[91],"that":[93,117],"extend":[94],"sequential":[99],"programs":[100],"concept":[101],"doing":[103],"control":[104],"state":[105],"partitioning.":[106],"technique":[108],"new":[110],"because":[111],"unique":[114],"model":[116],"uses.":[119],"Finally,":[120],"we":[121],"integrate":[125],"these":[126],"concepts":[127],"using":[128],"suitable":[130],"intermediate":[131],"called":[134],"process":[136],"graph.":[137]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}