{"id":"https://openalex.org/W2063471382","doi":"https://doi.org/10.1002/scj.4690271102","title":"Design of logic circuits with wired\u2010logic utilizing transduction method","display_name":"Design of logic circuits with wired\u2010logic utilizing transduction method","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W2063471382","doi":"https://doi.org/10.1002/scj.4690271102","mag":"2063471382"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690271102","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690271102","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068612356","display_name":"Shigeru Yamashita","orcid":"https://orcid.org/0000-0002-2279-4644"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shigeru Yamashita","raw_affiliation_strings":["Faculty of Engineering, Kyoto University, Kyoto University, Kyoto, Japan 606","Shigeru Yamashita:  was born in Ashiya, Japan, on August 31, 1970. He received his B.E. and M.E. degrees in Information Science from Kyoto University, Kyoto, Japan, in 1993 and 1995, respectively. In 1995, he joined NIIT Communication Science Laboratories, where he has been engaged in research on the computer aided design of digital systems and computer architecture. He is a member of the Information Processing Society of japan"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Kyoto University, Kyoto University, Kyoto, Japan 606","institution_ids":["https://openalex.org/I22299242"]},{"raw_affiliation_string":"Shigeru Yamashita:  was born in Ashiya, Japan, on August 31, 1970. He received his B.E. and M.E. degrees in Information Science from Kyoto University, Kyoto, Japan, in 1993 and 1995, respectively. In 1995, he joined NIIT Communication Science Laboratories, where he has been engaged in research on the computer aided design of digital systems and computer architecture. He is a member of the Information Processing Society of japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103702858","display_name":"Yahiko Kambayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yahiko Kambayashi","raw_affiliation_strings":["Faculty of Engineering, Kyoto University, Kyoto University, Kyoto, Japan 606","Yahiko Kambayashi:  received his B.E., M.E. and Ph.D. degrees in Electronic Engineering from Kyoto University, Kyoto, Japan, in 1965, 1967, and 1970, respectively. From 1970 to 1971 he was a Research Associate at Kyoto University. From 1971 to 1973 he was a Visiting Research Associate at the University of Illinois, Urbana. From 1973 to 1984 he was with the Department of Information Science, Kyoto University. In 1984 he became a Professor at the Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, Japan. Since 1990 he has been a Professor at Kyoto University and is currently working at the Department of Information Science. In 1979, he was a Visiting Professor at McGill University, Montreal, P.Q., Canada, and in 1984 was a Visiting Professor at Wuhan University, Wuhan, China. His research interests include logic design, switching theory, automata theory, and database theory. Dr. Kambayashi was a Chairman of SIGDBS (database systems) of the Information Processing society of Japan (IPSI). He was a Chairman of SIGCOMP (computation theory) of the Institute of Electronics, Information and Communication Engineers of Japan (IEICET). He was also a member of the board of IPS. He is a senior member of the Institute of Electrical and Electronics Engineers (IEEE), a member of IEICEI, IPSJ and the Association for Computing Machinery (ACM). He was an associate of ACM TODS (Transaction on Database Systems). He is currently a vice-chair of ACM Tokyo/Japan Chapter, and a member of the editorial board of several international journals. He has also organized several international conferences"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Kyoto University, Kyoto University, Kyoto, Japan 606","institution_ids":["https://openalex.org/I22299242"]},{"raw_affiliation_string":"Yahiko Kambayashi:  received his B.E., M.E. and Ph.D. degrees in Electronic Engineering from Kyoto University, Kyoto, Japan, in 1965, 1967, and 1970, respectively. From 1970 to 1971 he was a Research Associate at Kyoto University. From 1971 to 1973 he was a Visiting Research Associate at the University of Illinois, Urbana. From 1973 to 1984 he was with the Department of Information Science, Kyoto University. In 1984 he became a Professor at the Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, Japan. Since 1990 he has been a Professor at Kyoto University and is currently working at the Department of Information Science. In 1979, he was a Visiting Professor at McGill University, Montreal, P.Q., Canada, and in 1984 was a Visiting Professor at Wuhan University, Wuhan, China. His research interests include logic design, switching theory, automata theory, and database theory. Dr. Kambayashi was a Chairman of SIGDBS (database systems) of the Information Processing society of Japan (IPSI). He was a Chairman of SIGCOMP (computation theory) of the Institute of Electronics, Information and Communication Engineers of Japan (IEICET). He was also a member of the board of IPS. He is a senior member of the Institute of Electrical and Electronics Engineers (IEEE), a member of IEICEI, IPSJ and the Association for Computing Machinery (ACM). He was an associate of ACM TODS (Transaction on Database Systems). He is currently a vice-chair of ACM Tokyo/Japan Chapter, and a member of the editorial board of several international journals. He has also organized several international conferences","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036195592","display_name":"Saburo Muroga","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saburo Muroga","raw_affiliation_strings":["Department of Computer Science, University of Illinois, Urbana, Illinois, USA","Sabum Muroga:  was born in Numazu, Japan, in 1925. He received his Electrical Engineering degree from Tokyo University, Tokyo, Japan, in 1947. After working with the Railway Technical Laboratories and the Radio Regulatory Commission, he joined the staff of the Electrical Communication Laboratories, Nippon Telegraph and Telephone Publich Corporation, in 1951. There he was engaged in research on information theory. He was later in charge of the design, construction, and operation of MUSASINO-1, the first universal digital computer with parametrons in Japan. In 1960, he joined the Research Staff of IBM Thomas J. Watson Research Center, Yorktown Heights, NY. Since 1964 he has been a Professor of Computer Science and Electrical Engineering, Department of Computer Science, University of Illinois, Urbana, working on logic design automation for VLSI chips. He has published over 100 papers and several books on pulse modulation theory, narrow-band voice transmission systems, information theory, computer organization, threshold logic, file-memory addressing, integer programming, logic design, switching theory, and VLSICAD. Books titled Threshold Logic and Its Applications (1979), Logic Design and Switching Theoty (1979), and VLSI Sysrem Design (1982), all published by Wiley, are among these. Dr. Muroga is a member of the Association for Computing Machinery, the Information Processing Society of Japan, and the Institute of Electronics and Communication Engineers of Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Illinois, Urbana, Illinois, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"Sabum Muroga:  was born in Numazu, Japan, in 1925. He received his Electrical Engineering degree from Tokyo University, Tokyo, Japan, in 1947. After working with the Railway Technical Laboratories and the Radio Regulatory Commission, he joined the staff of the Electrical Communication Laboratories, Nippon Telegraph and Telephone Publich Corporation, in 1951. There he was engaged in research on information theory. He was later in charge of the design, construction, and operation of MUSASINO-1, the first universal digital computer with parametrons in Japan. In 1960, he joined the Research Staff of IBM Thomas J. Watson Research Center, Yorktown Heights, NY. Since 1964 he has been a Professor of Computer Science and Electrical Engineering, Department of Computer Science, University of Illinois, Urbana, working on logic design automation for VLSI chips. He has published over 100 papers and several books on pulse modulation theory, narrow-band voice transmission systems, information theory, computer organization, threshold logic, file-memory addressing, integer programming, logic design, switching theory, and VLSICAD. Books titled Threshold Logic and Its Applications (1979), Logic Design and Switching Theoty (1979), and VLSI Sysrem Design (1982), all published by Wiley, are among these. Dr. Muroga is a member of the Association for Computing Machinery, the Information Processing Society of Japan, and the Institute of Electronics and Communication Engineers of Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5068612356"],"corresponding_institution_ids":["https://openalex.org/I22299242"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17015547,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"27","issue":"11","first_page":"19","last_page":"28"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6634713411331177},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.643602728843689},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6074491739273071},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5978140234947205},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5569500923156738},{"id":"https://openalex.org/keywords/nor-logic","display_name":"NOR logic","score":0.4825007915496826},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.47170400619506836},{"id":"https://openalex.org/keywords/or-gate","display_name":"OR gate","score":0.43736958503723145},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.42623576521873474},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41961216926574707},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4000224471092224},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.36556705832481384},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32916444540023804},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.310539186000824},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17052039504051208},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13991209864616394}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6634713411331177},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.643602728843689},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6074491739273071},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5978140234947205},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5569500923156738},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.4825007915496826},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.47170400619506836},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.43736958503723145},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.42623576521873474},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41961216926574707},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4000224471092224},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.36556705832481384},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32916444540023804},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.310539186000824},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17052039504051208},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13991209864616394},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690271102","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690271102","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2037931040","https://openalex.org/W2064924231","https://openalex.org/W2133085302","https://openalex.org/W2134426126","https://openalex.org/W2146686891"],"related_works":["https://openalex.org/W2762653771","https://openalex.org/W2765195743","https://openalex.org/W4321519815","https://openalex.org/W1827076955","https://openalex.org/W2904118089","https://openalex.org/W3046672745","https://openalex.org/W1576731273","https://openalex.org/W1979361505","https://openalex.org/W1017999001","https://openalex.org/W2118713399"],"abstract_inverted_index":{"Abstract":[0],"Wired\u2010logic":[1],"is":[2,50,92,106,113,137,155],"especially":[3],"useful":[4],"when":[5],"designing":[6],"fan\u2010in":[7,90],"restricted":[8],"logic":[9],"circuits":[10,46,66,122],"which":[11,112],"are":[12,123],"implemented":[13],"with":[14],"bipolar":[15],"and":[16,64,80],"MOS":[17],"transistors.":[18],"There":[19],"is,":[20],"however,":[21],"little":[22],"published":[23],"on":[24,98],"the":[25,29,33,43,55,68,74,89,103,130,141,149,159],"subject":[26],"outside":[27],"of":[28,41,45,57,77,120,132,151],"work":[30],"done":[31],"by":[32,47,125],"present":[34],"authors.":[35],"In":[36],"this":[37,152],"paper,":[38,153],"a":[39,60],"method":[40,53,70,105],"reducing":[42],"levels":[44,119],"utilizing":[48,62],"Wired\u2010Logic":[49,63],"presented.":[51,94],"The":[52,118],"restricts":[54],"number":[56],"fanins":[58],"for":[59,88,148],"gate":[61],"transforms":[65],"using":[67,85],"transduction":[69],"optimization.":[71],"To":[72],"attain":[73],"proper":[75],"combination":[76],"NOR":[78,101],"gates":[79,87],"Wired\u2010OR":[81,86,126],"gates,":[82,127],"an":[83,114],"algorithm":[84],"restriction":[91],"also":[93],"By":[95],"performing":[96],"experiments":[97],"third":[99],"level":[100],"circuits,":[102],"proposed":[104],"comparable":[107],"to":[108,139,157],"Generalized":[109],"Serial":[110],"Duplication":[111],"efficient":[115],"serial":[116],"duplication.":[117],"most":[121],"reduced":[124],"thereby":[128],"demonstrating":[129],"efficiency":[131],"Wired\u2010Logic.":[133],"Although":[134],"connection":[135],"length":[136],"important":[138],"LSI,":[140],"cost":[142,160],"function":[143],"simplifies":[144],"circuit":[145],"levels.":[146],"Hence,":[147],"purposes":[150],"analysis":[154],"expanded":[156],"include":[158],"function.":[161]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
