{"id":"https://openalex.org/W1973837392","doi":"https://doi.org/10.1002/scj.4690260701","title":"Fault\u2010tolerant associate memories","display_name":"Fault\u2010tolerant associate memories","publication_year":1995,"publication_date":"1995-01-01","ids":{"openalex":"https://openalex.org/W1973837392","doi":"https://doi.org/10.1002/scj.4690260701","mag":"1973837392"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690260701","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690260701","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037946206","display_name":"Eiji Fujiwara","orcid":"https://orcid.org/0000-0002-1581-2680"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]},{"id":"https://openalex.org/I4210141265","display_name":"National Institute of Quality","ror":"https://ror.org/03ks20z28","country_code":"PE","type":"facility","lineage":["https://openalex.org/I4210141265"]}],"countries":["JP","PE"],"is_corresponding":false,"raw_author_name":"Eiji Fujiwara","raw_affiliation_strings":["Eui Fujiwara received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970, respectively, and his Dr. of Eng. degree in 1981, all from Tokyo Institute of Technology. In 1970, he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988, he joined the Department of Computer Science, Tokyo Institute of Technology as an Associate Professor. In 1990, he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies, the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers, fault-tolerant memories, VLSI defect-toleranceand WSI systems. He is a co-author of Error Control Coding for Computer Systems (Prentice-Hall1989), EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society, Japan","Eui Fujiwara: received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970, respectively, and his Dr. of Eng. degree in 1981, all from Tokyo Institute of Technology. In 1970, he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988, he joined the Department of Computer Science, Tokyo Institute of Technology as an Associate Professor. In 1990, he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies, the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers, fault-tolerant memories, VLSI defect-toleranceand WSI systems. He is a co-author of Error Control Coding for Computer Systems (Prentice-Hall1989), EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society, Japan","Faculty of Engineering, Tokyo Institute of Technology, Tokyo, Japan 152","Eui Fujiwara:  received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970, respectively, and his Dr. of Eng. degree in 1981, all from Tokyo Institute of Technology. In 1970, he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988, he joined the Department of Computer Science, Tokyo Institute of Technology as an Associate Professor. In 1990, he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies, the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers, fault-tolerant memories, VLSI defect-toleranceand WSI systems. He is a co-author of Error Control Coding for Computer Systems (Prentice-Hall1989), EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eui Fujiwara received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970, respectively, and his Dr. of Eng. degree in 1981, all from Tokyo Institute of Technology. In 1970, he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988, he joined the Department of Computer Science, Tokyo Institute of Technology as an Associate Professor. In 1990, he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies, the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers, fault-tolerant memories, VLSI defect-toleranceand WSI systems. He is a co-author of Error Control Coding for Computer Systems (Prentice-Hall1989), EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society, Japan","institution_ids":["https://openalex.org/I4210141265"]},{"raw_affiliation_string":"Eui Fujiwara: received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970, respectively, and his Dr. of Eng. degree in 1981, all from Tokyo Institute of Technology. In 1970, he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988, he joined the Department of Computer Science, Tokyo Institute of Technology as an Associate Professor. In 1990, he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies, the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers, fault-tolerant memories, VLSI defect-toleranceand WSI systems. He is a co-author of Error Control Coding for Computer Systems (Prentice-Hall1989), EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society, Japan","institution_ids":["https://openalex.org/I4210141265"]},{"raw_affiliation_string":"Faculty of Engineering, Tokyo Institute of Technology, Tokyo, Japan 152","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Eui Fujiwara:  received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970, respectively, and his Dr. of Eng. degree in 1981, all from Tokyo Institute of Technology. In 1970, he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988, he joined the Department of Computer Science, Tokyo Institute of Technology as an Associate Professor. In 1990, he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies, the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers, fault-tolerant memories, VLSI defect-toleranceand WSI systems. He is a co-author of Error Control Coding for Computer Systems (Prentice-Hall1989), EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society, Japan","institution_ids":["https://openalex.org/I4210141265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062932752","display_name":"Tsuyoshi Tanaka","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tsuyoshi Tanaka","raw_affiliation_strings":["Faculty of Engineering, Tokyo Institute of Technology, Tokyo, Japan 152","Tsuyoshi Tanaka received his B.S. degree in Electronic Engineering in 1993 from Tokyo Institute of Technology. He is currently in the Master's program of the Department of Computer Science, Tokyo Institute of Technology. His research interest includes the wafer-scale integration systems","Tsuyoshi Tanaka: received his B.S. degree in Electronic Engineering in 1993 from Tokyo Institute of Technology. He is currently in the Master's program of the Department of Computer Science, Tokyo Institute of Technology. His research interest includes the wafer-scale integration systems","Tsuyoshi Tanaka:  received his B.S. degree in Electronic Engineering in 1993 from Tokyo Institute of Technology. He is currently in the Master's program of the Department of Computer Science, Tokyo Institute of Technology. His research interest includes the wafer-scale integration systems"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Tokyo Institute of Technology, Tokyo, Japan 152","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Tsuyoshi Tanaka received his B.S. degree in Electronic Engineering in 1993 from Tokyo Institute of Technology. He is currently in the Master's program of the Department of Computer Science, Tokyo Institute of Technology. His research interest includes the wafer-scale integration systems","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Tsuyoshi Tanaka: received his B.S. degree in Electronic Engineering in 1993 from Tokyo Institute of Technology. He is currently in the Master's program of the Department of Computer Science, Tokyo Institute of Technology. His research interest includes the wafer-scale integration systems","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Tsuyoshi Tanaka:  received his B.S. degree in Electronic Engineering in 1993 from Tokyo Institute of Technology. He is currently in the Master's program of the Department of Computer Science, Tokyo Institute of Technology. His research interest includes the wafer-scale integration systems","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.09411446,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"26","issue":"7","first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/translation-lookaside-buffer","display_name":"Translation lookaside buffer","score":0.807471752166748},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7161802053451538},{"id":"https://openalex.org/keywords/byte","display_name":"Byte","score":0.6730722188949585},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6128594279289246},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5755292773246765},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5259131193161011},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5134268999099731},{"id":"https://openalex.org/keywords/content-addressable-memory","display_name":"Content-addressable memory","score":0.4725871980190277},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.43304771184921265},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4319758713245392},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4277298152446747},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39323732256889343},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2003861963748932},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.1767827570438385},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.14102765917778015},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10594320297241211}],"concepts":[{"id":"https://openalex.org/C116007543","wikidata":"https://www.wikidata.org/wiki/Q1071403","display_name":"Translation lookaside buffer","level":4,"score":0.807471752166748},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7161802053451538},{"id":"https://openalex.org/C43364308","wikidata":"https://www.wikidata.org/wiki/Q8799","display_name":"Byte","level":2,"score":0.6730722188949585},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6128594279289246},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5755292773246765},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5259131193161011},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5134268999099731},{"id":"https://openalex.org/C53442348","wikidata":"https://www.wikidata.org/wiki/Q745101","display_name":"Content-addressable memory","level":3,"score":0.4725871980190277},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.43304771184921265},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4319758713245392},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4277298152446747},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39323732256889343},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2003861963748932},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.1767827570438385},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.14102765917778015},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10594320297241211},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690260701","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690260701","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1533071485","https://openalex.org/W1993004270","https://openalex.org/W2015620405","https://openalex.org/W2016625431","https://openalex.org/W2026329829","https://openalex.org/W2059718621","https://openalex.org/W2125140079","https://openalex.org/W2136849670","https://openalex.org/W2147168629","https://openalex.org/W2155635853"],"related_works":["https://openalex.org/W1983621239","https://openalex.org/W2357767623","https://openalex.org/W2373076786","https://openalex.org/W2068933159","https://openalex.org/W2023744230","https://openalex.org/W2561621772","https://openalex.org/W1597512145","https://openalex.org/W1968760107","https://openalex.org/W2183082740","https://openalex.org/W2019678150"],"abstract_inverted_index":{"Abstract":[0],"Because":[1],"of":[2,5,20,44,47,54,58,235],"its":[3],"capability":[4,209],"high\u2010speed":[6],"search,":[7],"the":[8,45,55,59,63,69,99,103,107,111,121,128,132,135,143,156,165,185,215],"associative":[9],"memory":[10,187],"(CAM)":[11],"is":[12,41,106],"expected":[13],"to":[14,120],"be":[15],"used":[16],"in":[17,102,134,139,164,168,184,198],"a":[18,182],"variety":[19],"information":[21],"processing":[22],"systems.":[23],"In":[24],"this":[25,199],"paper,":[26],"novel":[27],"fault\u2010tolerant":[28,70,216],"techniques":[29,71],"which":[30,40,97,109],"are":[31,36,66,91,201],"effective":[32],"for":[33,38,72],"on\u2010line":[34],"use":[35],"proposed":[37,197],"TLB":[39,56,217],"an":[42],"example":[43],"application":[46],"CAM.":[48],"First,":[49],"fault":[50,232],"and":[51,62,75,88,115,137,154,161,189,206,227],"error":[52,148,207],"models":[53],"consisting":[57],"CAM":[60,104,113,136],"part":[61,65,105,114],"SRAM":[64,140],"clarified.":[67],"Then,":[68],"these":[73],"faults":[74],"errors,":[76],"such":[77],"as":[78],"distance":[79,94],"separable":[80,95],"technique,":[81,83],"cod\u2010ing":[82],"simplified":[84,171],"1\u2010out\u2010of\u2010":[85,172],"n":[86,173],"check":[87,174],"graceful":[89,179],"degradation,":[90],"proposed.":[92],"The":[93,124,170,178,195,211],"technique":[96,126],"encodes":[98],"data":[100,133,166],"stored":[101,167],"one":[108],"masks":[110],"faulty":[112,186],"prevents":[116,190],"errors":[117,163],"from":[118,192,203],"propagating":[119],"subsequent":[122],"circuits.":[123],"coding":[125],"checks":[127],"one\u2010to\u2010one":[129],"correspondence":[130],"between":[131],"those":[138],"by":[141],"using":[142],"SEC\u2010DED":[144],"code":[145],"with":[146,218,239],"byte":[147],"detection":[149,208,233],"capability,":[150],"i.e.,":[151],"SEC\u2010DED\u2010SbED":[152],"code,":[153],"at":[155],"same":[157],"time":[158],"it":[159,191],"detects":[160],"corrects":[162],"SRAM.":[169],"processes":[175],"association":[176],"errors.":[177],"degradation":[180],"gives":[181,230],"flag":[183],"section":[188],"being":[193],"used.":[194],"methods":[196],"paper":[200],"evaluated":[202],"area":[204,242],"augmentation":[205],"perspectives.":[210],"results":[212],"show":[213],"that":[214],"32":[219,223],"virtual":[220],"address":[221,225],"bits,":[222],"physical":[224],"bits":[226],"128":[228],"entries":[229],"single":[231],"probability":[234],"nearly":[236],"99":[237],"percent":[238,241],"28":[240],"increase.":[243]},"counts_by_year":[],"updated_date":"2026-06-23T06:36:01.041984","created_date":"2025-10-10T00:00:00"}
