{"id":"https://openalex.org/W2023535967","doi":"https://doi.org/10.1002/scj.4690260201","title":"A study of network logic for wafer\u2010scale parallel\u2010access memory and a yield analysis","display_name":"A study of network logic for wafer\u2010scale parallel\u2010access memory and a yield analysis","publication_year":1995,"publication_date":"1995-01-01","ids":{"openalex":"https://openalex.org/W2023535967","doi":"https://doi.org/10.1002/scj.4690260201","mag":"2023535967"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690260201","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690260201","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056233837","display_name":"Koichi Yamashita","orcid":"https://orcid.org/0000-0002-6226-3194"},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]},{"id":"https://openalex.org/I3132238960","display_name":"Institute of Electrical and Electronics Engineers","ror":"https://ror.org/01n002310","country_code":"US","type":"education","lineage":["https://openalex.org/I3132238960"]}],"countries":["JP","US"],"is_corresponding":false,"raw_author_name":"Koichi Yamashita","raw_affiliation_strings":["Fujitsu Laboratories LTD., Atsugi, Japan 243","Koichi Yamashita received his B.E. and M.E. degrees in 1980 and 1981, respectively, in Electrical Engineering from Kobe University. In 1982 he joined Fujitsu Laboratories. He has been engaged in R&D on large scale, quick turn-around time Gate Arrays, and Wafer-Scale Integration. He is a member of the IEEE Computer Society and the Institute of Electronics, Information, and Communication Engineers of Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories LTD., Atsugi, Japan 243","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Koichi Yamashita received his B.E. and M.E. degrees in 1980 and 1981, respectively, in Electrical Engineering from Kobe University. In 1982 he joined Fujitsu Laboratories. He has been engaged in R&D on large scale, quick turn-around time Gate Arrays, and Wafer-Scale Integration. He is a member of the IEEE Computer Society and the Institute of Electronics, Information, and Communication Engineers of Japan","institution_ids":["https://openalex.org/I3132238960"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109135283","display_name":"Shohei Ikehara","orcid":null},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]},{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP","US"],"is_corresponding":false,"raw_author_name":"Shohei Ikehara","raw_affiliation_strings":["Fujitsu Limited, Kawasaki, Japan 211","Shohei Ikehara received his degrees in Electrical Communications and Electronics Engineering from Electrical Communications Univ. in 1975, and in the same year he joined Fujitsu. He took part in the development of Mass Storage devices for Super Computers, and expansion of memory capacity of storage devices. He is a member of the Information Processing Society of Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Limited, Kawasaki, Japan 211","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Shohei Ikehara received his degrees in Electrical Communications and Electronics Engineering from Electrical Communications Univ. in 1975, and in the same year he joined Fujitsu. He took part in the development of Mass Storage devices for Super Computers, and expansion of memory capacity of storage devices. He is a member of the Information Processing Society of Japan","institution_ids":["https://openalex.org/I117023288"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13208571,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"26","issue":"2","first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.6305840611457825},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6151043176651001},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.612998366355896},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5911307334899902},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5552157163619995},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5144875049591064},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.5135757923126221},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5042260885238647},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5025277137756348},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.49514856934547424},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.48647066950798035},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4576725959777832},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4483109414577484},{"id":"https://openalex.org/keywords/megabit","display_name":"Megabit","score":0.4347551465034485},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4218406677246094},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.40700721740722656},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3533109724521637},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2077799141407013},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18956822156906128},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16899511218070984}],"concepts":[{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.6305840611457825},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6151043176651001},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.612998366355896},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5911307334899902},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5552157163619995},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5144875049591064},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.5135757923126221},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5042260885238647},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5025277137756348},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.49514856934547424},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.48647066950798035},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4576725959777832},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4483109414577484},{"id":"https://openalex.org/C185177783","wikidata":"https://www.wikidata.org/wiki/Q3332814","display_name":"Megabit","level":2,"score":0.4347551465034485},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4218406677246094},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.40700721740722656},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3533109724521637},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2077799141407013},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18956822156906128},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16899511218070984},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690260201","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690260201","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1563537685","https://openalex.org/W2008859755","https://openalex.org/W2046045084","https://openalex.org/W2060733183","https://openalex.org/W2067954102","https://openalex.org/W2119510613","https://openalex.org/W2134375099","https://openalex.org/W2137816402"],"related_works":["https://openalex.org/W2019238062","https://openalex.org/W1690307066","https://openalex.org/W2491097902","https://openalex.org/W2056436264","https://openalex.org/W4285257158","https://openalex.org/W2898989424","https://openalex.org/W4238754064","https://openalex.org/W2493772236","https://openalex.org/W3006048143","https://openalex.org/W2023535967"],"abstract_inverted_index":{"Abstract":[0],"The":[1,37],"paper":[2],"describes":[3],"wafer\u2010scale":[4,22,91],"memory":[5,23,33,85,92,95,105,111],"design":[6],"with":[7],"network":[8],"logic":[9],"based":[10],"on":[11,87],"switching":[12],"register":[13],"circuit":[14],"(SW\u2010REG),":[15],"and":[16,35,46,64,70],"defect":[17,77],"tolerance":[18,78],"schemes.":[19,79],"Such":[20],"a":[21,32],"is":[24,49,113],"an":[25,88],"array":[26],"of":[27,31,42,61],"chips,":[28],"each":[29,47],"consisting":[30],"core":[34,86,106],"SW\u2010REG.":[36],"SW\u2010REG":[38,74],"links":[39],"neighboring":[40],"chips":[41],"the":[43,53],"same":[44],"column,":[45],"column":[48],"independently":[50],"accessible":[51],"from":[52],"outside.":[54],"Monte":[55],"Carlo":[56],"simulation":[57],"demonstrated":[58],"that":[59],"addition":[60],"driver":[62],"transistors":[63],"spare":[65],"lines":[66,72],"to":[67,73],"common":[68],"signals,":[69],"bypass":[71],"are":[75],"optimum":[76],"When":[80],"using":[81],"64":[82],"Mbit":[83],"DRAM":[84],"8\u2010inch":[89],"wafer,":[90],"gives":[93],"higher":[94,110],"capacity":[96,112],"than":[97],"corresponding":[98],"discrete":[99],"chip":[100],"system:":[101],"for":[102],"5":[103],"percent":[104],"yield,":[107],"13":[108],"times":[109],"achieved.":[114]},"counts_by_year":[],"updated_date":"2026-06-23T06:36:01.041984","created_date":"2025-10-10T00:00:00"}