{"id":"https://openalex.org/W2014653483","doi":"https://doi.org/10.1002/scj.4690250901","title":"Estimating the performance of multiple functional unit and pipelined processor using statistical instruction dependencies","display_name":"Estimating the performance of multiple functional unit and pipelined processor using statistical instruction dependencies","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W2014653483","doi":"https://doi.org/10.1002/scj.4690250901","mag":"2014653483"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690250901","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690250901","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087047502","display_name":"Yasuo Kinouchi","orcid":"https://orcid.org/0000-0002-3558-0442"},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yasuo Kinouchi","raw_affiliation_strings":["NTT Communication Switching Laboratories, Musashino, Japan 180","Yasuo Kinouchi received his B.S. and M.S. degrees in 1969 and 1971, respectively, from Waseda Univ. and affiliated with NTT. He is engaged in research and development of hardware systems. Presently, Senior Research Engineer, Intelligent Network Systems Laboratory, NTT Comm. Switching Laboratories. He is a member of Inf. Proc. Society"],"affiliations":[{"raw_affiliation_string":"NTT Communication Switching Laboratories, Musashino, Japan 180","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"Yasuo Kinouchi received his B.S. and M.S. degrees in 1969 and 1971, respectively, from Waseda Univ. and affiliated with NTT. He is engaged in research and development of hardware systems. Presently, Senior Research Engineer, Intelligent Network Systems Laboratory, NTT Comm. Switching Laboratories. He is a member of Inf. Proc. Society","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032222802","display_name":"Takayuki Hoshiko","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takayuki Hoshiko","raw_affiliation_strings":["Network Systems Development Center, NTT, Tokyo, Japan 108","Takayuki Hoshiko received his B.S. and M.S. degrees in 1972 and 1974, respectively, from Kyushu Univ. and affiliated with NTT. He is engaged in research and practical applications of DIPS hardware system, as well as system investigation of the open architecture systems. Presently, Senior Manager, Inf. Comm. Systems Dep., NTT Customer Systems Develop. Dep. He is a member of Inf. Proc. Society"],"affiliations":[{"raw_affiliation_string":"Network Systems Development Center, NTT, Tokyo, Japan 108","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"Takayuki Hoshiko received his B.S. and M.S. degrees in 1972 and 1974, respectively, from Kyushu Univ. and affiliated with NTT. He is engaged in research and practical applications of DIPS hardware system, as well as system investigation of the open architecture systems. Presently, Senior Manager, Inf. Comm. Systems Dep., NTT Customer Systems Develop. Dep. He is a member of Inf. Proc. Society","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054266410","display_name":"Kouichi Inamori","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kouichi Inamori","raw_affiliation_strings":["Integrated Communications Systems Headquarters, NTT, Kawasaki, Japan 210","Kouichi Inamori received his B.S. degree in 1967 from Waseda Univ. and affiliated with NTT Elect. Comm. Lab. He is engaged in R&D of computer architecture, facsimile communication system and graphic communication. Presently, he is engaged in research on the interactive multimedia information communication services. He is a member of Inf. Proc. Society"],"affiliations":[{"raw_affiliation_string":"Integrated Communications Systems Headquarters, NTT, Kawasaki, Japan 210","institution_ids":[]},{"raw_affiliation_string":"Kouichi Inamori received his B.S. degree in 1967 from Waseda Univ. and affiliated with NTT Elect. Comm. Lab. He is engaged in R&D of computer architecture, facsimile communication system and graphic communication. Presently, he is engaged in research on the interactive multimedia information communication services. He is a member of Inf. Proc. Society","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5087047502"],"corresponding_institution_ids":["https://openalex.org/I2251713219"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12731872,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"9","first_page":"1","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8692063093185425},{"id":"https://openalex.org/keywords/dependency","display_name":"Dependency (UML)","score":0.6969910860061646},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.5389905571937561},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.5253331661224365},{"id":"https://openalex.org/keywords/relation","display_name":"Relation (database)","score":0.5028874278068542},{"id":"https://openalex.org/keywords/histogram","display_name":"Histogram","score":0.4865218997001648},{"id":"https://openalex.org/keywords/variable","display_name":"Variable (mathematics)","score":0.44756758213043213},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42547911405563354},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3581092655658722},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.26868385076522827},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19346073269844055},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.1448420286178589},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14132028818130493},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09006783366203308},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.08980551362037659}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8692063093185425},{"id":"https://openalex.org/C19768560","wikidata":"https://www.wikidata.org/wiki/Q320727","display_name":"Dependency (UML)","level":2,"score":0.6969910860061646},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.5389905571937561},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.5253331661224365},{"id":"https://openalex.org/C25343380","wikidata":"https://www.wikidata.org/wiki/Q277521","display_name":"Relation (database)","level":2,"score":0.5028874278068542},{"id":"https://openalex.org/C53533937","wikidata":"https://www.wikidata.org/wiki/Q185020","display_name":"Histogram","level":3,"score":0.4865218997001648},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.44756758213043213},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42547911405563354},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3581092655658722},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.26868385076522827},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19346073269844055},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.1448420286178589},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14132028818130493},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09006783366203308},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.08980551362037659},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690250901","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690250901","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W239283595","https://openalex.org/W1555915743","https://openalex.org/W1984277858","https://openalex.org/W1996583445","https://openalex.org/W2031337049","https://openalex.org/W2042617557","https://openalex.org/W2074175208","https://openalex.org/W2107068041","https://openalex.org/W2114876342","https://openalex.org/W2120114655","https://openalex.org/W2520487307","https://openalex.org/W4231413340"],"related_works":["https://openalex.org/W2000547159","https://openalex.org/W2122760055","https://openalex.org/W2789964135","https://openalex.org/W2152596151","https://openalex.org/W2121109048","https://openalex.org/W3007374139","https://openalex.org/W2151554479","https://openalex.org/W2898441718","https://openalex.org/W199866330","https://openalex.org/W37057355"],"abstract_inverted_index":{"Abstract":[0],"This":[1],"paper":[2],"considers":[3],"the":[4,7,16,23,29,37,39,54,59,68,71,74,77,85,89,95,98,104,115,121,129],"processor":[5,72,105],"with":[6],"parallel":[8],"operation":[9],"and":[10,28,53,97,120],"lookahead":[11],"control":[12],"functions":[13],"based":[14,87],"on":[15,88,103],"real\u2010time":[17],"system":[18],"program.":[19],"The":[20,92,112],"relation":[21],"between":[22,47],"logical":[24],"dependencies":[25],"among":[26],"instructions":[27,50,75],"performance":[30,126],"improvement":[31,127],"is":[32,51,56,65,80,107,118,123,134],"analyzed.":[33],"With":[34],"respect":[35],"to":[36],"dependency,":[38],"number":[40,99],"of":[41,70,84,94,100,114,125,131],"dynamic":[42],"steps":[43],"that":[44],"are":[45],"processed":[46],"logically":[48],"dependent":[49],"considered,":[52],"histogram":[55],"examined":[57],"in":[58,82],"program":[60],"actually":[61],"run.":[62],"A":[63],"method":[64,117],"devised":[66],"wherein":[67],"behavior":[69],"executing":[73],"following":[76],"written":[78],"order":[79,130],"represented":[81],"terms":[83],"probability":[86],"statistical":[90],"data.":[91],"effects":[93],"dependency":[96],"functional":[101],"units":[102],"also":[106],"evaluated":[108,124],"by":[109],"a":[110],"simulation.":[111],"validity":[113],"proposed":[116],"verified":[119],"effect":[122],"when":[128],"instruction":[132],"execution":[133],"made":[135],"variable.":[136]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
