{"id":"https://openalex.org/W2159996605","doi":"https://doi.org/10.1002/scj.4690200407","title":"Simulation processor \u201cSP\u201d","display_name":"Simulation processor \u201cSP\u201d","publication_year":1989,"publication_date":"1989-01-01","ids":{"openalex":"https://openalex.org/W2159996605","doi":"https://doi.org/10.1002/scj.4690200407","mag":"2159996605"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690200407","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690200407","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043457676","display_name":"Hiroshi Yamada","orcid":"https://orcid.org/0000-0002-0536-5581"},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]},{"id":"https://openalex.org/I4210097274","display_name":"Tashkent Institute of Architecture and Civil Engineering","ror":"https://ror.org/00phht511","country_code":"UZ","type":"education","lineage":["https://openalex.org/I4210097274"]},{"id":"https://openalex.org/I4210157642","display_name":"Institute of Automation","ror":"https://ror.org/056qj1t15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210157642","https://openalex.org/I78650965"]}],"countries":["DE","JP","UZ"],"is_corresponding":false,"raw_author_name":"Hiroshi Yamada","raw_affiliation_strings":["Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","Hiroshi Yamada graduated in 1952 from Dept. Phys., Fac. Sci., University of Tokyo. He then joined Fujitsu Limited (then Fuji Comm. Equip.) where he worked in computer design and development. He became Executive Director of Fujitsu Laboratories, Ltd., in 1979. Currently, he is Deputy President. He is a member of Inf. Proc. Soc. Jap.; Office Autom. Soc.; and Soc. Artif. Intell. He is the author of Computer Architecture and CAD of VLSI Computer","Office Autom. Soc","Hiroshi Yamada graduated in 1952 from Dept. Phys., Fac. Sci., University of Tokyo. He then joined Fujitsu Limited (then Fuji Comm. Equip.) where he worked in computer design and development. He became Executive Director of Fujitsu Laboratories, Ltd., in 1979. Currently, he is Deputy President. He is a member of Inf. Proc. Soc. Jap","Soc. Artif. Intell. He is the author of Computer Architecture and CAD of VLSI Computer"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Hiroshi Yamada graduated in 1952 from Dept. Phys., Fac. Sci., University of Tokyo. He then joined Fujitsu Limited (then Fuji Comm. Equip.) where he worked in computer design and development. He became Executive Director of Fujitsu Laboratories, Ltd., in 1979. Currently, he is Deputy President. He is a member of Inf. Proc. Soc. Jap.; Office Autom. Soc.; and Soc. Artif. Intell. He is the author of Computer Architecture and CAD of VLSI Computer","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Office Autom. Soc","institution_ids":["https://openalex.org/I4210157642"]},{"raw_affiliation_string":"Hiroshi Yamada graduated in 1952 from Dept. Phys., Fac. Sci., University of Tokyo. He then joined Fujitsu Limited (then Fuji Comm. Equip.) where he worked in computer design and development. He became Executive Director of Fujitsu Laboratories, Ltd., in 1979. Currently, he is Deputy President. He is a member of Inf. Proc. Soc. Jap","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Soc. Artif. Intell. He is the author of Computer Architecture and CAD of VLSI Computer","institution_ids":["https://openalex.org/I4210097274"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055792891","display_name":"Fumiyasu Hirose","orcid":null},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Fumiyasu Hirose","raw_affiliation_strings":["Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","Fumiyasu Hirose graduated in 1976 from Dept. Electronic Eng., Fac. Eng., Tokyo Inst. of Technology, and obtained a Master's degree from there in 1978. He then joined Fujitsu Laboratories, Ltd., where he worked in CAD research. He was a Visiting Researcher in 1980\u20131981 in the Dept. Computer Sci., Stanford University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Fumiyasu Hirose graduated in 1976 from Dept. Electronic Eng., Fac. Eng., Tokyo Inst. of Technology, and obtained a Master's degree from there in 1978. He then joined Fujitsu Laboratories, Ltd., where he worked in CAD research. He was a Visiting Researcher in 1980\u20131981 in the Dept. Computer Sci., Stanford University","institution_ids":["https://openalex.org/I2252096349"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085825444","display_name":"Junichi Niitsuma","orcid":null},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Junichi Niitsuma","raw_affiliation_strings":["Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","Junichi Niitsuma graduated in 1984 from Dept. Electrical Eng., Hokkaido University, and joined Fujitsu Laboratories, Ltd., where he worked on developing logic simulation machines"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Junichi Niitsuma graduated in 1984 from Dept. Electrical Eng., Hokkaido University, and joined Fujitsu Laboratories, Ltd., where he worked on developing logic simulation machines","institution_ids":["https://openalex.org/I2252096349"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011251623","display_name":"Tatsuya Shindo","orcid":null},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tatsuya Shindo","raw_affiliation_strings":["Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","Tatsuya Shindo graduated in 1983 from Dept. Elect. Comm., Sch. Sci. Tech., Waseda University, and joined Fujitsu Laboratories, Ltd., where he worked in CAD research. He received the Shinohara Encour. Prize in 1985"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories, Ltd., Kawasaki, Japan 211","institution_ids":["https://openalex.org/I2252096349"]},{"raw_affiliation_string":"Tatsuya Shindo graduated in 1983 from Dept. Elect. Comm., Sch. Sci. Tech., Waseda University, and joined Fujitsu Laboratories, Ltd., where he worked in CAD research. He received the Shinohara Encour. Prize in 1985","institution_ids":["https://openalex.org/I2252096349"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9951,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.77997192,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"20","issue":"4","first_page":"71","last_page":"79"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7922897338867188},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7663027048110962},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.5973950624465942},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.5669916272163391},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5273821353912354},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4597509205341339},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43689677119255066},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.4319716691970825},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4077637791633606},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39721208810806274},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3294675946235657},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13430166244506836}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7922897338867188},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7663027048110962},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.5973950624465942},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.5669916272163391},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5273821353912354},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4597509205341339},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43689677119255066},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.4319716691970825},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4077637791633606},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39721208810806274},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3294675946235657},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13430166244506836},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690200407","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690200407","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1970112123","https://openalex.org/W1988286948","https://openalex.org/W2006168247","https://openalex.org/W2050831047","https://openalex.org/W2144977947","https://openalex.org/W2148752144","https://openalex.org/W2164357943","https://openalex.org/W2522538732","https://openalex.org/W3098506267","https://openalex.org/W4231288534","https://openalex.org/W4236231374","https://openalex.org/W4246174232","https://openalex.org/W4252142323","https://openalex.org/W4253013447"],"related_works":["https://openalex.org/W2017449983","https://openalex.org/W4231839681","https://openalex.org/W2077986289","https://openalex.org/W4251160711","https://openalex.org/W1971201388","https://openalex.org/W2340724640","https://openalex.org/W2765012215","https://openalex.org/W2072573989","https://openalex.org/W2347708070","https://openalex.org/W2096997494"],"abstract_inverted_index":{"Abstract":[0],"The":[1,27,60,120],"continuing":[2],"development":[3],"of":[4,37,40,104,111,128,142],"large\u2010scale":[5],"and":[6,90],"complicated":[7],"computer":[8],"systems":[9],"has":[10],"created":[11],"an":[12],"increasing":[13],"demand":[14],"for":[15,52,66,85],"fast":[16],"logic":[17,25,132],"simulation":[18,56,67],"which":[19,34,68,139],"can":[20,117],"locate":[21],"errors":[22],"in":[23,42,114,138],"the":[24,44,50,58,102,109,126,129],"design.":[26],"authors":[28],"have":[29],"devised":[30,82],"a":[31,54,63,80,97,131],"new":[32,55],"scheme":[33],"makes":[35],"use":[36],"memory":[38,143],"instead":[39],"registers":[41],"controlling":[43],"pipeline":[45,83],"system.":[46],"This":[47],"idea":[48],"formed":[49],"basis":[51],"developing":[53],"processor,":[57],"\u201cSP\u201d.":[59],"SP":[61],"is":[62],"system":[64],"dedicated":[65],"performs":[69],"parallel":[70,115],"processing":[71,105,116],"using":[72],"up":[73],"to":[74,108],"64":[75],"gate":[76],"processors":[77,95],"(GP).":[78],"Using":[79],"newly":[81],"control":[84],"each":[86],"processor":[87],"delivers":[88],"high\u2010speed":[89,98],"inexpensive":[91],"simulation.":[92],"By":[93],"combining":[94],"with":[96,125,134],"switch":[99],"called":[100],"ET,":[101],"degradation":[103],"speed":[106],"due":[107],"delay":[110],"information":[112],"transmission":[113],"be":[118,145],"prevented.":[119],"desired":[121],"goal":[122],"was":[123],"achieved":[124],"construction":[127],"SP,":[130],"circuit":[133],"4":[135],"million":[136],"gates":[137],"32":[140],"Mbytes":[141],"could":[144],"simulated":[146],"at":[147],"high":[148],"speed.":[149]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
