{"id":"https://openalex.org/W2041951979","doi":"https://doi.org/10.1002/scj.4690200207","title":"An implementation of multiple\u2010valued logic circuit with cmos multiple\u2010valued output gates","display_name":"An implementation of multiple\u2010valued logic circuit with cmos multiple\u2010valued output gates","publication_year":1989,"publication_date":"1989-01-01","ids":{"openalex":"https://openalex.org/W2041951979","doi":"https://doi.org/10.1002/scj.4690200207","mag":"2041951979"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690200207","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690200207","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003979188","display_name":"Izumi Sakata","orcid":null},"institutions":[{"id":"https://openalex.org/I184937672","display_name":"Chubu University","ror":"https://ror.org/02sps0775","country_code":"JP","type":"education","lineage":["https://openalex.org/I184937672"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Izumi Sakata","raw_affiliation_strings":["Faculty of Engineering, Chubu University, Kasugai, Japan 487","Izumi Sakata graduated in 1977 from Dept. Electrical Eng., Fac. Eng., Nagoya Institute of Technology, and obtained his Master's degree from there in 1979. In 1980, he was an Assistant in Eng. Sci. Gr., Fac. Eng., Chubu University. He is engaged primarily in research on multiple-valued logic"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Chubu University, Kasugai, Japan 487","institution_ids":["https://openalex.org/I184937672"]},{"raw_affiliation_string":"Izumi Sakata graduated in 1977 from Dept. Electrical Eng., Fac. Eng., Nagoya Institute of Technology, and obtained his Master's degree from there in 1979. In 1980, he was an Assistant in Eng. Sci. Gr., Fac. Eng., Chubu University. He is engaged primarily in research on multiple-valued logic","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5003979188"],"corresponding_institution_ids":["https://openalex.org/I184937672"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14669796,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"20","issue":"2","first_page":"67","last_page":"77"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9818000197410583,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9818000197410583,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9771000146865845,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9664999842643738,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6347622275352478},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5421044230461121},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5354620814323425},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5270212888717651},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5133571028709412},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.498779296875},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.48191264271736145},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.459919810295105},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4531247913837433},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4500945210456848},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.42874860763549805},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41827523708343506},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38130664825439453},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37736454606056213},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3377534747123718},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.27226391434669495},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16327181458473206},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12088024616241455},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10545036196708679}],"concepts":[{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6347622275352478},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5421044230461121},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5354620814323425},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5270212888717651},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5133571028709412},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.498779296875},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.48191264271736145},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.459919810295105},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4531247913837433},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4500945210456848},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.42874860763549805},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41827523708343506},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38130664825439453},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37736454606056213},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3377534747123718},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.27226391434669495},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16327181458473206},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12088024616241455},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10545036196708679},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690200207","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690200207","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8399999737739563}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321555","display_name":"Chubu University","ror":"https://ror.org/02sps0775"},{"id":"https://openalex.org/F4320322312","display_name":"Kansai University","ror":"https://ror.org/03xg1f311"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W40265213","https://openalex.org/W2000709659","https://openalex.org/W2043294591","https://openalex.org/W2130149272","https://openalex.org/W2167317202"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2118487491","https://openalex.org/W2152533674","https://openalex.org/W1593138522","https://openalex.org/W2155174752","https://openalex.org/W2991771859","https://openalex.org/W2356714888","https://openalex.org/W1553855433","https://openalex.org/W1828408332","https://openalex.org/W2006855068"],"abstract_inverted_index":{"Abstract":[0],"With":[1],"the":[2,19,22,26,35,48,56,59,62,66,79,103,106,120,123,128,131,134,142,147,151,156,169,179,185,190,193,201,208,220],"progress":[3],"of":[4,37,47,61,90,108,122],"high\u2010density":[5,23],"information":[6,29],"handling":[7],"technology,":[8],"multiple\u2010valued":[9,28,40,49,71,76,124,135,144,160,194,221],"logic":[10,50,125,148,164,222],"is":[11,53,153,175,187,215,225],"considered":[12],"interesting.":[13],"Studies":[14],"have":[15],"been":[16],"made":[17,216],"on":[18],"applications":[20],"to":[21,55,101,114,133,192,218,229],"VLSI":[24],"and":[25,43,65,111,162,227],"optimally":[27],"processing":[30],"systems.":[31],"This":[32],"paper":[33],"considers":[34],"use":[36],"a":[38,75],"CMOS":[39,70],"output":[41,72,77,97,136,195],"gate,":[42],"proposes":[44],"an":[45],"implementation":[46],"circuit,":[51,223],"which":[52,224],"suited":[54,228],"integration":[57,63],"from":[58,78,141,155],"viewpoints":[60],"density":[64],"power":[67],"consumption.":[68],"The":[69],"gate":[73,104,137,196],"produces":[74],"predetermined":[80],"number":[81],"(":[82],"n":[83,87,116,181],"\u2010":[84],"1":[85],"for":[86,178,206],"\u2010valued":[88,117,182],"case)":[89],"binary":[91,163],"inputs.":[92],"Compared":[93],"with":[94,159],"similar":[95],"multiple\u2010level":[96],"circuits":[98],"proposed":[99,129,170],"up":[100],"now,":[102],"has":[105],"feature":[107],"simple":[109,226],"structure":[110],"easy":[112],"correspondence":[113],"arbitrary":[115,180],"function.":[118],"In":[119],"design":[121,186],"circuit":[126,149,158],"by":[127,168],"method,":[130],"inputs":[132,152,161,191],"are":[138,172,211],"determined":[139],"first":[140],"required":[143],"output.":[145],"Then":[146],"satisfying":[150],"constructed":[154],"literal":[157],"circuits.":[165],"Design":[166],"examples":[167],"method":[171],"presented.":[173],"It":[174],"shown":[176],"especially":[177],"case":[183],"that":[184],"simplified":[188],"since":[189],"can":[197],"be":[198],"represented":[199],"in":[200],"general":[202,209],"form.":[203],"Several":[204],"rules":[205],"deriving":[207],"form":[210],"described.":[212],"Finally,":[213],"it":[214],"possible":[217],"implement":[219],"integration.":[230]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
