{"id":"https://openalex.org/W2079741609","doi":"https://doi.org/10.1002/scj.4690200202","title":"A prolog machine based on vlsi algorithms","display_name":"A prolog machine based on vlsi algorithms","publication_year":1989,"publication_date":"1989-01-01","ids":{"openalex":"https://openalex.org/W2079741609","doi":"https://doi.org/10.1002/scj.4690200202","mag":"2079741609"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690200202","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690200202","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006679744","display_name":"Yasuro Shobatake","orcid":null},"institutions":[{"id":"https://openalex.org/I203951103","display_name":"Keio University","ror":"https://ror.org/02kn6nx58","country_code":"JP","type":"education","lineage":["https://openalex.org/I203951103"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yasuro Shobatake","raw_affiliation_strings":["Faculty of Science and Technology, Keio University, Yokohama, Japan 223","Yasuro Shobatake graduated in 1985 from Dept. Electrical Eng., Fac. Sci. Tech., Keio University, and obtained a Master's degree in 1987. He then affiliated with R & D Center, Toshiba Corp. He is engaged presently in R & D of ATM communication network. His primary interest is in symbol-processing-oriented architecture and interconnection networks. He is a member of Inf. Proc. Soc. Jap.; and ACM","Yasuro Shobatake graduated in 1985 from Dept. Electrical Eng., Fac. Sci. Tech., Keio University, and obtained a Master's degree in 1987. He then affiliated with R & D Center, Toshiba Corp. He is engaged presently in R & D of ATM communication network. His primary interest is in symbol-processing-oriented architecture and interconnection networks. He is a member of Inf. Proc. Soc. Jap"],"affiliations":[{"raw_affiliation_string":"Faculty of Science and Technology, Keio University, Yokohama, Japan 223","institution_ids":["https://openalex.org/I203951103"]},{"raw_affiliation_string":"Yasuro Shobatake graduated in 1985 from Dept. Electrical Eng., Fac. Sci. Tech., Keio University, and obtained a Master's degree in 1987. He then affiliated with R & D Center, Toshiba Corp. He is engaged presently in R & D of ATM communication network. His primary interest is in symbol-processing-oriented architecture and interconnection networks. He is a member of Inf. Proc. Soc. Jap.; and ACM","institution_ids":[]},{"raw_affiliation_string":"Yasuro Shobatake graduated in 1985 from Dept. Electrical Eng., Fac. Sci. Tech., Keio University, and obtained a Master's degree in 1987. He then affiliated with R & D Center, Toshiba Corp. He is engaged presently in R & D of ATM communication network. His primary interest is in symbol-processing-oriented architecture and interconnection networks. He is a member of Inf. Proc. Soc. Jap","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026911323","display_name":"Hideo Aiso","orcid":null},"institutions":[{"id":"https://openalex.org/I203951103","display_name":"Keio University","ror":"https://ror.org/02kn6nx58","country_code":"JP","type":"education","lineage":["https://openalex.org/I203951103"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hideo Aiso","raw_affiliation_strings":["Faculty of Science and Technology, Keio University, Yokohama, Japan 223","Hideo Aiso graduated in 1955 from Dept. Electrical Eng., Fac. Eng., Keio University, and obtained a Master's degree in 1957. He has a Dr. of Engineering degree. Dr. Aiso was an Assistant on the Fac. Eng., Osaka University, and then joined Electrotechnical Lab., Min. Int. Trade and Indust. He is engaged in R & D on transistorized computers. He was at Computer Lab., Univ. of Illinois, USA, from 1960\u20131961. Since 1970, he has been a Professor in the Dept. Elect. Eng., Fac. Eng., Keio University. He is the author of Computer Architecture (Iwanami Publ.) and other books. He is a member of IEEE; and ACM","Hideo Aiso graduated in 1955 from Dept. Electrical Eng., Fac. Eng., Keio University, and obtained a Master's degree in 1957. He has a Dr. of Engineering degree. Dr. Aiso was an Assistant on the Fac. Eng., Osaka University, and then joined Electrotechnical Lab., Min. Int. Trade and Indust. He is engaged in R & D on transistorized computers. He was at Computer Lab., Univ. of Illinois, USA, from 1960\u20131961. Since 1970, he has been a Professor in the Dept. Elect. Eng., Fac. Eng., Keio University. He is the author of Computer Architecture (Iwanami Publ.) and other books. He is a member of IEEE"],"affiliations":[{"raw_affiliation_string":"Faculty of Science and Technology, Keio University, Yokohama, Japan 223","institution_ids":["https://openalex.org/I203951103"]},{"raw_affiliation_string":"Hideo Aiso graduated in 1955 from Dept. Electrical Eng., Fac. Eng., Keio University, and obtained a Master's degree in 1957. He has a Dr. of Engineering degree. Dr. Aiso was an Assistant on the Fac. Eng., Osaka University, and then joined Electrotechnical Lab., Min. Int. Trade and Indust. He is engaged in R & D on transistorized computers. He was at Computer Lab., Univ. of Illinois, USA, from 1960\u20131961. Since 1970, he has been a Professor in the Dept. Elect. Eng., Fac. Eng., Keio University. He is the author of Computer Architecture (Iwanami Publ.) and other books. He is a member of IEEE; and ACM","institution_ids":[]},{"raw_affiliation_string":"Hideo Aiso graduated in 1955 from Dept. Electrical Eng., Fac. Eng., Keio University, and obtained a Master's degree in 1957. He has a Dr. of Engineering degree. Dr. Aiso was an Assistant on the Fac. Eng., Osaka University, and then joined Electrotechnical Lab., Min. Int. Trade and Indust. He is engaged in R & D on transistorized computers. He was at Computer Lab., Univ. of Illinois, USA, from 1960\u20131961. Since 1970, he has been a Professor in the Dept. Elect. Eng., Fac. Eng., Keio University. He is the author of Computer Architecture (Iwanami Publ.) and other books. He is a member of IEEE","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5006679744"],"corresponding_institution_ids":["https://openalex.org/I203951103"],"apc_list":null,"apc_paid":null,"fwci":0.5366,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.73666667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"20","issue":"2","first_page":"15","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.98580002784729,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8285161256790161},{"id":"https://openalex.org/keywords/prolog","display_name":"Prolog","score":0.6709921956062317},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5984446406364441},{"id":"https://openalex.org/keywords/symbol","display_name":"Symbol (formal)","score":0.5596106648445129},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5193639397621155},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5177932977676392},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5110741853713989},{"id":"https://openalex.org/keywords/expression","display_name":"Expression (computer science)","score":0.4772922098636627},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.46774154901504517},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4573480784893036},{"id":"https://openalex.org/keywords/data-processing","display_name":"Data processing","score":0.44436416029930115},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.4254392385482788},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.28580567240715027},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.17871278524398804},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1572936475276947},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08470109105110168}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8285161256790161},{"id":"https://openalex.org/C81721847","wikidata":"https://www.wikidata.org/wiki/Q163468","display_name":"Prolog","level":2,"score":0.6709921956062317},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5984446406364441},{"id":"https://openalex.org/C134400042","wikidata":"https://www.wikidata.org/wiki/Q2372244","display_name":"Symbol (formal)","level":2,"score":0.5596106648445129},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5193639397621155},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5177932977676392},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5110741853713989},{"id":"https://openalex.org/C90559484","wikidata":"https://www.wikidata.org/wiki/Q778379","display_name":"Expression (computer science)","level":2,"score":0.4772922098636627},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.46774154901504517},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4573480784893036},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.44436416029930115},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.4254392385482788},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.28580567240715027},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.17871278524398804},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1572936475276947},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08470109105110168},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690200202","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690200202","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1503162431","https://openalex.org/W2016929153"],"related_works":["https://openalex.org/W2595172197","https://openalex.org/W2084856301","https://openalex.org/W2127970246","https://openalex.org/W1001352512","https://openalex.org/W4382618745","https://openalex.org/W2885125400","https://openalex.org/W1989889224","https://openalex.org/W2748922771","https://openalex.org/W1987128138","https://openalex.org/W2126622512"],"abstract_inverted_index":{"Abstract":[0],"This":[1],"paper":[2],"proposes":[3],"a":[4,20,29,61,109,150,157],"Prolog":[5,154],"direct":[6],"executer":[7],"called":[8,63,100],"PMV\u20102.":[9],"To":[10,45,107],"alleviate":[11],"the":[12,33,36,47,51,86,90,98,120,131,145],"von":[13],"Neumann":[14],"bottleneck,":[15],"PMV\u20102":[16,115],"is":[17,116,138,143],"provided":[18],"with":[19,68,156],"number":[21,111],"of":[22,26,85,112,134,149],"processing":[23,34,55,81,91,113,132],"elements,":[24,35,56,114],"each":[25],"which":[27,76,142],"stores":[28],"term":[30],"symbol.":[31],"Using":[32],"operations":[37],"for":[38,49,80],"terms":[39],"can":[40,94],"be":[41,95],"executed":[42],"in":[43],"parallel.":[44],"simplify":[46],"algorithm":[48],"mapping":[50],"tree\u2010structured":[52,87],"data":[53,57,67,88],"onto":[54,73],"are":[58,71],"represented":[59],"by":[60,140],"format":[62],"symbol\u2010line":[64],"expression.":[65],"Tree\u2010structured":[66],"this":[69],"expression":[70],"mapped":[72],"an":[74],"array":[75,93],"has":[77,126],"straight\u2010line":[78],"arrangement":[79],"elements.":[82],"The":[83],"configuration":[84],"on":[89,119],"element":[92],"modified":[96],"using":[97],"methods":[99],"Partial":[101,105],"Global":[102],"Communication":[103],"and":[104],"Shift.":[106],"implement":[108],"large":[110],"constructed":[117],"based":[118],"VLSI":[121],"algorithms.":[122],"A":[123],"performance":[124],"evaluation":[125],"been":[127],"made,":[128],"revealing":[129],"that":[130,148],"speed":[133],"approximately":[135],"450":[136],"kLips":[137],"obtained":[139],"PMV\u20102,":[141],"nearly":[144],"same":[146],"as":[147],"presently":[151],"available":[152],"high\u2010speed":[153],"system":[155],"compiler.":[158]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
