{"id":"https://openalex.org/W2019777842","doi":"https://doi.org/10.1002/scj.4690190108","title":"Reconfiguration of a fault\u2010tolerant rectangular systolic array","display_name":"Reconfiguration of a fault\u2010tolerant rectangular systolic array","publication_year":1988,"publication_date":"1988-01-01","ids":{"openalex":"https://openalex.org/W2019777842","doi":"https://doi.org/10.1002/scj.4690190108","mag":"2019777842"},"language":"en","primary_location":{"id":"doi:10.1002/scj.4690190108","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690190108","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000412527","display_name":"Y. Suzuki","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yoshinao Suzuki","raw_affiliation_strings":["NEC Corporation, Tokyo, Japan 108"],"affiliations":[{"raw_affiliation_string":"NEC Corporation, Tokyo, Japan 108","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112718564","display_name":"Tomio Hirata","orcid":null},"institutions":[{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tomio Hirata","raw_affiliation_strings":["Faculty of Engineering, Nagoya University, Nagoya, Japan 464"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Nagoya University, Nagoya, Japan 464","institution_ids":["https://openalex.org/I60134161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109865597","display_name":"Masaharu Imai","orcid":null},"institutions":[{"id":"https://openalex.org/I136259955","display_name":"Toyohashi University of Technology","ror":"https://ror.org/04ezg6d83","country_code":"JP","type":"education","lineage":["https://openalex.org/I136259955"]},{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masaharu Imai","raw_affiliation_strings":["Faculty of Engineering, Toyohashi University of Technology, Toyohashi, Japan 440","Masaru Imai received BS in Electrical Engineering from Nagoya University in 1974 and a"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Toyohashi University of Technology, Toyohashi, Japan 440","institution_ids":["https://openalex.org/I136259955"]},{"raw_affiliation_string":"Masaru Imai received BS in Electrical Engineering from Nagoya University in 1974 and a","institution_ids":["https://openalex.org/I60134161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111575379","display_name":"Masafumi Yamashita","orcid":null},"institutions":[{"id":"https://openalex.org/I113306721","display_name":"Hiroshima University","ror":"https://ror.org/03t78wx29","country_code":"JP","type":"education","lineage":["https://openalex.org/I113306721"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masafumi Yamashita","raw_affiliation_strings":["Faculty of Engineering, Hiroshima University, Higashi-Hiroshima, Japan 774","Masafumi Yamashita received BS in Information from Kyoto University in 1974, an MS degree there in 1977. He received a PhD from Nagoya University in 1980. He was an assistant at Toyohashi University of Technology and currently he is an assistant professor, Faculty of Engineering, Hiroshima University. He was avisiting professor at Simon Frazer University. He has been working on dispersed processing algorithms, optimization for combinations, and fundamentals for computer architecture"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Hiroshima University, Higashi-Hiroshima, Japan 774","institution_ids":["https://openalex.org/I113306721"]},{"raw_affiliation_string":"Masafumi Yamashita received BS in Information from Kyoto University in 1974, an MS degree there in 1977. He received a PhD from Nagoya University in 1980. He was an assistant at Toyohashi University of Technology and currently he is an assistant professor, Faculty of Engineering, Hiroshima University. He was avisiting professor at Simon Frazer University. He has been working on dispersed processing algorithms, optimization for combinations, and fundamentals for computer architecture","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113496426","display_name":"Toshihide Ibaraki","orcid":null},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshihide Ibaraki","raw_affiliation_strings":["Faculty of Engineering, Kyoto University, Kyoto, Japan 606","Toshihide Ibaraki received BS in Electrical Engineering from Kyoto University in 1963 and an MS degree there in 1965. He became an assistant at Faculty of Engineering, Kyoto University in 1969 and an assistant professor there in 1973. In 1983 he became a professor at Toyohashi University of Technology and in 1985 he became a professor at Kyoto University. He has been working on optimization for combinations and complexities of calculations. He was a visiting faculty staff at University of Illinois, University of Waterloo, Simon Frazer University, and Rutgers University. Among his published books are Theory for Optimization f o r Combinations and Optimization for Combinations: Centered on Limited Branchings. In 1973 he received the Inada Award from the I.E.C.E.J. He holds a degree of doctor of engineering"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Kyoto University, Kyoto, Japan 606","institution_ids":["https://openalex.org/I22299242"]},{"raw_affiliation_string":"Toshihide Ibaraki received BS in Electrical Engineering from Kyoto University in 1963 and an MS degree there in 1965. He became an assistant at Faculty of Engineering, Kyoto University in 1969 and an assistant professor there in 1973. In 1983 he became a professor at Toyohashi University of Technology and in 1985 he became a professor at Kyoto University. He has been working on optimization for combinations and complexities of calculations. He was a visiting faculty staff at University of Illinois, University of Waterloo, Simon Frazer University, and Rutgers University. Among his published books are Theory for Optimization f o r Combinations and Optimization for Combinations: Centered on Limited Branchings. In 1973 he received the Inada Award from the I.E.C.E.J. He holds a degree of doctor of engineering","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5000412527"],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.13710088,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"19","issue":"1","first_page":"79","last_page":"89"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9484420418739319},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.7525661587715149},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7101393342018127},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6629349589347839},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6215612888336182},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.6014481782913208},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.6005136966705322},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5447536110877991},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4553414583206177},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4159398674964905},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2673022449016571},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.226851224899292},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.18931230902671814},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06928384304046631},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.049564749002456665}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9484420418739319},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.7525661587715149},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7101393342018127},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6629349589347839},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6215612888336182},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.6014481782913208},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.6005136966705322},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5447536110877991},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4553414583206177},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4159398674964905},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2673022449016571},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.226851224899292},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.18931230902671814},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06928384304046631},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.049564749002456665},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/scj.4690190108","is_oa":false,"landing_page_url":"https://doi.org/10.1002/scj.4690190108","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1522841521","https://openalex.org/W1967575124","https://openalex.org/W1977920491","https://openalex.org/W2011039300","https://openalex.org/W2046826146","https://openalex.org/W2121881146","https://openalex.org/W2133009808","https://openalex.org/W2137816402","https://openalex.org/W2148631003","https://openalex.org/W2157529519","https://openalex.org/W2171896511","https://openalex.org/W3139452672","https://openalex.org/W4212788429","https://openalex.org/W4213214460","https://openalex.org/W4244540812","https://openalex.org/W6681971441"],"related_works":["https://openalex.org/W2165091308","https://openalex.org/W1950809481","https://openalex.org/W2130594209","https://openalex.org/W2102525122","https://openalex.org/W2153096481","https://openalex.org/W2148616436","https://openalex.org/W2085988155","https://openalex.org/W2158463942","https://openalex.org/W4306316843","https://openalex.org/W2036953450"],"abstract_inverted_index":{"Abstract":[0],"Fault\u2010tolerant":[1],"designs":[2,18],"which":[3],"incorporate":[4],"redundancy":[5],"to":[6,66],"improve":[7],"the":[8,30,62],"yields":[9],"of":[10,33,47,52],"VLSI":[11],"chips":[12],"are":[13,23,56],"well":[14],"known.":[15],"In":[16],"such":[17],"flaws":[19],"in":[20],"a":[21,34,39,44],"chip":[22],"excluded":[24],"by":[25],"reconfiguration.":[26],"This":[27],"paper":[28],"discusses":[29],"reconfiguration":[31,55],"problem":[32,63],"rectangular":[35,40],"systolic":[36,41],"array:":[37],"Given":[38],"array,":[42],"construct":[43],"flawless":[45],"array":[46],"maximum":[48],"size.":[49],"Three":[50],"levels":[51],"constraints":[53],"on":[54],"considered,":[57],"and":[58,69],"for":[59],"each":[60],"constraint":[61],"is":[64,73],"proved":[65],"be":[67],"NP\u2010complete":[68],"an":[70],"approximation":[71],"algorithm":[72],"proposed.":[74]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
