{"id":"https://openalex.org/W2083271047","doi":"https://doi.org/10.1002/ett.4460050409","title":"VLSI implementation of a signal interpolator chip for high\u2010speed all\u2010digital data modems","display_name":"VLSI implementation of a signal interpolator chip for high\u2010speed all\u2010digital data modems","publication_year":1994,"publication_date":"1994-07-01","ids":{"openalex":"https://openalex.org/W2083271047","doi":"https://doi.org/10.1002/ett.4460050409","mag":"2083271047"},"language":"en","primary_location":{"id":"doi:10.1002/ett.4460050409","is_oa":false,"landing_page_url":"https://doi.org/10.1002/ett.4460050409","pdf_url":null,"source":{"id":"https://openalex.org/S4393917101","display_name":"European Transactions on Telecommunications","issn_l":"1124-318X","issn":["1124-318X","1541-8251"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"European Transactions on Telecommunications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068301009","display_name":"Marco Luise","orcid":"https://orcid.org/0000-0002-7291-0914"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Luise","raw_affiliation_strings":["Dipartimento di Ingegneria dell'Informazione, Universita\u0300 di Pisa Via Diotisalvi 2, 56126 Pisa - Italy","Dipartimento di Ingegneria dell'Informazione, Universit\u00e0 di Pisa, Via Diotisalvi 2, 56126 Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell'Informazione, Universita\u0300 di Pisa Via Diotisalvi 2, 56126 Pisa - Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria dell'Informazione, Universit\u00e0 di Pisa, Via Diotisalvi 2, 56126 Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027666807","display_name":"Roberto Roncella","orcid":"https://orcid.org/0000-0003-4087-9761"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Roberto Roncella","raw_affiliation_strings":["Dipartimento di Ingegneria dell'Informazione, Universita\u0300 di Pisa Via Diotisalvi 2, 56126 Pisa - Italy","Dipartimento di Ingegneria dell'Informazione, Universit\u00e0 di Pisa, Via Diotisalvi 2, 56126 Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell'Informazione, Universita\u0300 di Pisa Via Diotisalvi 2, 56126 Pisa - Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria dell'Informazione, Universit\u00e0 di Pisa, Via Diotisalvi 2, 56126 Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I108290504"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.2368214,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":"4","first_page":"475","last_page":"482"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7098903656005859},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6850022077560425},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6128745675086975},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5356813073158264},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.49306294322013855},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47350484132766724},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.469904363155365},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.4674331545829773},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.45896247029304504},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.45580530166625977},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4297485947608948},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4268205761909485},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4172332286834717},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3474227786064148},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3328478932380676},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20359355211257935},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15167200565338135},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.14808699488639832},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12711137533187866},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0882229208946228}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7098903656005859},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6850022077560425},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6128745675086975},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5356813073158264},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.49306294322013855},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47350484132766724},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.469904363155365},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.4674331545829773},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.45896247029304504},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.45580530166625977},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4297485947608948},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4268205761909485},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4172332286834717},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3474227786064148},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3328478932380676},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20359355211257935},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15167200565338135},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.14808699488639832},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12711137533187866},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0882229208946228},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/ett.4460050409","is_oa":false,"landing_page_url":"https://doi.org/10.1002/ett.4460050409","pdf_url":null,"source":{"id":"https://openalex.org/S4393917101","display_name":"European Transactions on Telecommunications","issn_l":"1124-318X","issn":["1124-318X","1541-8251"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"European Transactions on Telecommunications","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W581057811","https://openalex.org/W1837811341","https://openalex.org/W1876018024","https://openalex.org/W2046651563","https://openalex.org/W2061774327","https://openalex.org/W2063678701","https://openalex.org/W2120579245","https://openalex.org/W2139722549","https://openalex.org/W2144537848","https://openalex.org/W2147456588","https://openalex.org/W2161388663","https://openalex.org/W2162153812","https://openalex.org/W3036935753"],"related_works":["https://openalex.org/W2015155483","https://openalex.org/W2038682752","https://openalex.org/W2142131433","https://openalex.org/W2739720767","https://openalex.org/W2105613219","https://openalex.org/W2163915119","https://openalex.org/W1572837867","https://openalex.org/W2141748053","https://openalex.org/W1989850581","https://openalex.org/W2016344977"],"abstract_inverted_index":{"Abstract":[0],"This":[1],"paper":[2],"describes":[3],"the":[4,22,43,59,62,69,79,83,85,166,176],"structure":[5],"of":[6,46,58,61,68,82,88,144,161,171,178,186],"a":[7,33,39,55,65,120,133,141,182],"signal":[8],"interpolator":[9,125],"chip":[10,63,126,167],"to":[11],"be":[12],"used":[13],"in":[14],"medium\u2010to\u2010high":[15],"data":[16],"rate":[17,177],"digital":[18],"modems,":[19],"based":[20],"on":[21,32],"so\u2010called":[23],"\u201cSystolic":[24],"Macrocells\u201d":[25],"design":[26,122],"style.":[27],"In":[28,153],"particular,":[29,154],"we":[30,155],"focus":[31],"third\u2010order":[34],"polynomial":[35],"interpolation":[36],"algorithm,":[37],"as":[38,108],"good":[40],"trade\u2010off":[41],"between":[42],"contrasting":[44],"needs":[45],"high":[47],"accuracy":[48],"and":[49,96,104,110,139],"low":[50],"complexity/cost.":[51],"We":[52],"also":[53],"present":[54],"concise":[56],"description":[57,67],"architecture":[60],"through":[64],"functional":[66],"main":[70],"basic":[71,86],"systolic":[72,91],"macrocells":[73],"it":[74],"is":[75],"composed":[76,101],"of.":[77],"Despite":[78],"apparent":[80],"complexity":[81],"architecture,":[84],"cells":[87],"each":[89],"bit\u2010level":[90],"array":[92],"are":[93,99],"remarkably":[94],"simple":[95],"homogeneous:":[97],"they":[98],"mainly":[100],"by":[102],"delays":[103],"summing":[105],"elements":[106],"such":[107],"full":[109],"half":[111],"adders,":[112],"so":[113,164],"that":[114,165],"their":[115],"realization":[116],"does":[117],"not":[118],"represent":[119],"difficult":[121],"task.":[123],"The":[124],"has":[127],"been":[128],"completely":[129],"laid":[130],"out":[131],"assuming":[132],"1.2":[134],"\u03bc":[135],"m":[136],"CMOS":[137],"technology":[138],"occupies":[140],"silicon":[142],"area":[143],"5":[145],"\u00d7":[146],"4.5":[147],"mm":[148],"2":[149],",":[150],"pad":[151],"included.":[152],"envisage":[156],"an":[157],"operating":[158],"clock":[159],"frequency":[160],"70":[162],"MHz,":[163],"can":[168],"process":[169],"sequences":[170],"8":[172],"bit":[173],"words":[174],"at":[175],"17.5":[179],"MSamples/s":[180],"with":[181],"power":[183],"supply":[184],"requirement":[185],"less":[187],"than":[188],"0.5":[189],"W.":[190]},"counts_by_year":[],"updated_date":"2026-06-23T06:36:01.041984","created_date":"2025-10-10T00:00:00"}