{"id":"https://openalex.org/W2040062045","doi":"https://doi.org/10.1002/ett.4460030211","title":"The ATM shuffleout switching fabric: Design and implementation issues","display_name":"The ATM shuffleout switching fabric: Design and implementation issues","publication_year":1992,"publication_date":"1992-03-01","ids":{"openalex":"https://openalex.org/W2040062045","doi":"https://doi.org/10.1002/ett.4460030211","mag":"2040062045"},"language":"en","primary_location":{"id":"doi:10.1002/ett.4460030211","is_oa":false,"landing_page_url":"https://doi.org/10.1002/ett.4460030211","pdf_url":null,"source":{"id":"https://openalex.org/S4393917101","display_name":"European Transactions on Telecommunications","issn_l":"1124-318X","issn":["1124-318X","1541-8251"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"European Transactions on Telecommunications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073015939","display_name":"F. Masetti","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]},{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Francesco Masetti","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano Piazza Leonardo da Vinci 32, 20133 - Milano - Italy","Now at DEIS, Universita\u0300 di Bologna - Viale Risorgimento 2, 40136 - Bologna - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano Piazza Leonardo da Vinci 32, 20133 - Milano - Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Now at DEIS, Universita\u0300 di Bologna - Viale Risorgimento 2, 40136 - Bologna - Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034035400","display_name":"Achille Pattavina","orcid":"https://orcid.org/0000-0003-0015-9866"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Achille Pattavina","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano Piazza Leonardo da Vinci 32, 20133 - Milano - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano Piazza Leonardo da Vinci 32, 20133 - Milano - Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012043041","display_name":"Cesare Sironi","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cesare Sironi","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Milano Piazza Leonardo da Vinci 32, 20133 - Milano - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Milano Piazza Leonardo da Vinci 32, 20133 - Milano - Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073015939"],"corresponding_institution_ids":["https://openalex.org/I9360294","https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":1.4721,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.83439794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":"2","first_page":"157","last_page":"166"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.854775071144104},{"id":"https://openalex.org/keywords/multistage-interconnection-networks","display_name":"Multistage interconnection networks","score":0.7520025968551636},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7138537168502808},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6628663539886475},{"id":"https://openalex.org/keywords/label-switching","display_name":"Label switching","score":0.6479376554489136},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6132763624191284},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5959759950637817},{"id":"https://openalex.org/keywords/circuit-switching","display_name":"Circuit switching","score":0.5776891708374023},{"id":"https://openalex.org/keywords/lan-switching","display_name":"LAN switching","score":0.5134733319282532},{"id":"https://openalex.org/keywords/packet-switching","display_name":"Packet switching","score":0.4896300435066223},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4589333236217499},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.44581273198127747},{"id":"https://openalex.org/keywords/cut-through-switching","display_name":"Cut-through switching","score":0.43939071893692017},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35138237476348877},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2825380563735962},{"id":"https://openalex.org/keywords/burst-switching","display_name":"Burst switching","score":0.2760239839553833},{"id":"https://openalex.org/keywords/transmission-delay","display_name":"Transmission delay","score":0.20527708530426025},{"id":"https://openalex.org/keywords/multiprotocol-label-switching","display_name":"Multiprotocol Label Switching","score":0.07723134756088257}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.854775071144104},{"id":"https://openalex.org/C2776832011","wikidata":"https://www.wikidata.org/wiki/Q6935099","display_name":"Multistage interconnection networks","level":3,"score":0.7520025968551636},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7138537168502808},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6628663539886475},{"id":"https://openalex.org/C123467649","wikidata":"https://www.wikidata.org/wiki/Q1799397","display_name":"Label switching","level":4,"score":0.6479376554489136},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6132763624191284},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5959759950637817},{"id":"https://openalex.org/C74294265","wikidata":"https://www.wikidata.org/wiki/Q506273","display_name":"Circuit switching","level":2,"score":0.5776891708374023},{"id":"https://openalex.org/C185498113","wikidata":"https://www.wikidata.org/wiki/Q4503","display_name":"LAN switching","level":5,"score":0.5134733319282532},{"id":"https://openalex.org/C113508815","wikidata":"https://www.wikidata.org/wiki/Q193446","display_name":"Packet switching","level":3,"score":0.4896300435066223},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4589333236217499},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.44581273198127747},{"id":"https://openalex.org/C182437060","wikidata":"https://www.wikidata.org/wiki/Q383791","display_name":"Cut-through switching","level":5,"score":0.43939071893692017},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35138237476348877},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2825380563735962},{"id":"https://openalex.org/C180026317","wikidata":"https://www.wikidata.org/wiki/Q5000645","display_name":"Burst switching","level":4,"score":0.2760239839553833},{"id":"https://openalex.org/C108921912","wikidata":"https://www.wikidata.org/wiki/Q7834639","display_name":"Transmission delay","level":3,"score":0.20527708530426025},{"id":"https://openalex.org/C129880937","wikidata":"https://www.wikidata.org/wiki/Q677023","display_name":"Multiprotocol Label Switching","level":3,"score":0.07723134756088257},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1002/ett.4460030211","is_oa":false,"landing_page_url":"https://doi.org/10.1002/ett.4460030211","pdf_url":null,"source":{"id":"https://openalex.org/S4393917101","display_name":"European Transactions on Telecommunications","issn_l":"1124-318X","issn":["1124-318X","1541-8251"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"European Transactions on Telecommunications","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/664170","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/664170","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W72753072","https://openalex.org/W1479869265","https://openalex.org/W1572271588","https://openalex.org/W1989929342","https://openalex.org/W2070244621","https://openalex.org/W2099484701","https://openalex.org/W2151903999","https://openalex.org/W2155582739","https://openalex.org/W2162660799"],"related_works":["https://openalex.org/W2071685753","https://openalex.org/W2384540401","https://openalex.org/W2960233929","https://openalex.org/W2367206928","https://openalex.org/W2365899400","https://openalex.org/W1641662195","https://openalex.org/W2160514860","https://openalex.org/W1971294334","https://openalex.org/W2074449548","https://openalex.org/W1606001471"],"abstract_inverted_index":{"Abstract":[0],"This":[1],"paper":[2],"describes":[3],"the":[4,10,27,43,59,84,99,109,129,148],"design":[5,114,134],"and":[6,35,73,119,135],"implementation":[7,136],"aspects":[8],"of":[9,16,23,29,49,58,86,115,120,147],"Shuffleout":[11,131],"switch,":[12],"a":[13,30,36,92,116,121,144],"new":[14,37],"class":[15],"switching":[17,53,67,100,117],"fabric":[18,101],"architectures.":[19],"The":[20,111],"key":[21],"points":[22],"this":[24],"structure":[25],"are":[26,62],"adoption":[28],"memoryless":[31],"multistage":[32,45],"interconnection":[33,47,60,87],"network":[34,48,61,88],"packet":[38],"routing":[39],"strategy.":[40],"Compared":[41],"to":[42,128],"basic":[44,130],"shuffle":[46],"Shuffleout,":[50],"adopting":[51],"2\u00d74":[52],"elements,":[54,68],"three":[55],"other":[56],"architectures":[57,151],"described,":[63],"which":[64],"use":[65],"larger":[66],"that":[69,90],"is":[70,123,152],"4\u00d76,":[71],"3\u00d75":[72],"4\u00d78.":[74],"Adopting":[75],"these":[76],"upgraded":[77],"structures":[78],"aims":[79],"not":[80],"only":[81],"at":[82,105],"decreasing":[83],"number":[85],"stages":[89],"provide":[91],"given":[93],"cell":[94],"loss":[95],"probability,":[96],"thus":[97],"reducing":[98],"complexity,":[102],"but":[103],"also":[104],"improving":[106],"fairness":[107],"in":[108],"network.":[110],"VLSI":[112],"hardware":[113],"element":[118],"chip":[122],"then":[124],"described":[125],"with":[126,133],"reference":[127],"structure,":[132],"details":[137],"on":[138],"their":[139],"major":[140],"functional":[141],"blocks.":[142],"Finally":[143],"complexity":[145],"comparison":[146],"different":[149],"enhanced":[150],"assessed.":[153]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}