{"id":"https://openalex.org/W4408330015","doi":"https://doi.org/10.1002/cta.4514","title":"An SDPF RISC\u2010V Processor With 55.9% Dhrystone Improvement Using Two\u2010Stage Pseudo\u2010Pipelined Architecture for IoT Applications","display_name":"An SDPF RISC\u2010V Processor With 55.9% Dhrystone Improvement Using Two\u2010Stage Pseudo\u2010Pipelined Architecture for IoT Applications","publication_year":2025,"publication_date":"2025-03-05","ids":{"openalex":"https://openalex.org/W4408330015","doi":"https://doi.org/10.1002/cta.4514"},"language":"en","primary_location":{"id":"doi:10.1002/cta.4514","is_oa":true,"landing_page_url":"https://doi.org/10.1002/cta.4514","pdf_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.4514","source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.4514","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104162256","display_name":"Wenji Mo","orcid":null},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenji Mo","raw_affiliation_strings":["School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100442541","display_name":"Jingjing Liu","orcid":"https://orcid.org/0000-0001-5285-4997"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jingjing Liu","raw_affiliation_strings":["School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100375413","display_name":"Yuchen Wang","orcid":"https://orcid.org/0000-0003-1122-1119"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuchen Wang","raw_affiliation_strings":["School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100662276","display_name":"Feng Yan","orcid":"https://orcid.org/0009-0004-6963-2302"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Feng Yan","raw_affiliation_strings":["School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102699157","display_name":"Bingjun Xiong","orcid":null},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bingjun Xiong","raw_affiliation_strings":["School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102879698","display_name":"Jian Guan","orcid":"https://orcid.org/0000-0001-8684-8106"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Guan","raw_affiliation_strings":["School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Communication Engineering Sun Yat\u2010Sen University  Shenzhen China","institution_ids":["https://openalex.org/I157773358"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100442541"],"corresponding_institution_ids":["https://openalex.org/I157773358"],"apc_list":{"value":3660,"currency":"USD","value_usd":3660},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04298189,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"53","issue":"10","first_page":"5827","last_page":"5838"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.7465896010398865},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6643723249435425},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.569679856300354},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5621262788772583},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.526114284992218},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.46724581718444824},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4542740285396576},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35558104515075684},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.263286828994751}],"concepts":[{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.7465896010398865},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6643723249435425},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.569679856300354},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5621262788772583},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.526114284992218},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.46724581718444824},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4542740285396576},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35558104515075684},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.263286828994751},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/cta.4514","is_oa":true,"landing_page_url":"https://doi.org/10.1002/cta.4514","pdf_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.4514","source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1002/cta.4514","is_oa":true,"landing_page_url":"https://doi.org/10.1002/cta.4514","pdf_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.4514","source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G137698199","display_name":null,"funder_award_id":"62174181","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4408330015.pdf"},"referenced_works_count":23,"referenced_works":["https://openalex.org/W220440441","https://openalex.org/W1998525920","https://openalex.org/W2004340162","https://openalex.org/W2010635096","https://openalex.org/W2013275447","https://openalex.org/W2037279745","https://openalex.org/W2791224953","https://openalex.org/W2963255460","https://openalex.org/W2971948544","https://openalex.org/W2979287008","https://openalex.org/W3015634719","https://openalex.org/W3133748104","https://openalex.org/W3164403439","https://openalex.org/W4286571897","https://openalex.org/W4296682658","https://openalex.org/W4360605480","https://openalex.org/W4360605522","https://openalex.org/W4383113483","https://openalex.org/W4385080211","https://openalex.org/W4388561807","https://openalex.org/W4391020439","https://openalex.org/W4391892644","https://openalex.org/W4399997006"],"related_works":["https://openalex.org/W122453572","https://openalex.org/W4200599950","https://openalex.org/W2035206467","https://openalex.org/W4317937473","https://openalex.org/W4404991316","https://openalex.org/W2351011383","https://openalex.org/W2146879484","https://openalex.org/W4221002079","https://openalex.org/W1757458251","https://openalex.org/W1980898636"],"abstract_inverted_index":{"ABSTRACT":[0],"Embedded":[1],"Internet":[2],"of":[3,24,37,50,86,121],"Things":[4],"(IoT)":[5],"nodes":[6],"are":[7,41],"required":[8],"to":[9,34,76,211],"perform":[10],"lightweight":[11],"tasks":[12],"such":[13],"as":[14],"information":[15],"monitoring":[16],"and":[17,48,57,102,133,156,190],"simple":[18],"signal":[19],"processing.":[20],"A":[21],"crucial":[22],"component":[23],"low\u2010power":[25,31,63],"embedded":[26],"IoT":[27],"sensors":[28],"is":[29,112,128,169],"the":[30,35,45,51,55,68,83,87,116,122,139,150,162,209,216],"processor.":[32,52,124,201,220],"Due":[33],"constraints":[36],"operating":[38],"conditions,":[39],"there":[40],"stringent":[42],"requirements":[43],"on":[44,67],"power":[46,56,194,212],"consumption":[47,195],"area":[49,189],"To":[53,81],"minimize":[54],"area,":[58],"this":[59,94],"paper":[60,95],"proposes":[61,96],"a":[62,77,97,108,172,205],"RV32I":[64,219],"processor":[65,127,141,168],"based":[66],"RISC\u2010V":[69,154],"instruction":[70,105,119],"set":[71],"architecture":[72],"(ISA),":[73],"which":[74],"adheres":[75],"serial":[78,88],"data":[79,89],"path.":[80],"enhance":[82],"energy":[84],"efficiency":[85],"path":[90],"followed":[91],"(SDPF)":[92],"processor,":[93],"pseudo\u2010pipeline":[98,110],"architecture.":[99],"By":[100],"partitioning":[101],"combining":[103],"certain":[104],"lifecycle":[106],"tasks,":[107],"two\u2010stage":[109],"structure":[111],"implemented,":[113],"thereby":[114],"reducing":[115],"cycles":[117],"per":[118],"(CPI)":[120],"SDPF":[123,164,218],"The":[125,166,177],"proposed":[126,140,167],"designed":[129],"using":[130,171],"Verilog":[131],"HDL,":[132],"FPGA":[134],"prototype":[135],"validation":[136],"demonstrates":[137],"that":[138,182],"achieves":[142,204],"at":[143,185],"least":[144,186],"18%":[145],"fewer":[146],"resource":[147],"compared":[148,160,196,214],"with":[149,161,197,215],"traditional":[151,198],"parallel":[152,199],"32\u2010bit":[153,200],"processors":[155],"55.9%":[157],"performance":[158,210],"improvement":[159],"previous":[163,217],"processors.":[165],"implemented":[170],"standard":[173],"0.18\u2010\u03bcm":[174],"CMOS":[175],"process.":[176],"post\u2010layout":[178],"simulation":[179],"results":[180],"indicate":[181],"it":[183,203],"has":[184],"9.6%":[187],"less":[188],"37.5%":[191],"lower":[192],"dynamic":[193],"Additionally,":[202],"40.9%":[206],"increase":[207],"in":[208],"ratio":[213]},"counts_by_year":[],"updated_date":"2025-12-28T23:10:05.387466","created_date":"2025-10-10T00:00:00"}