{"id":"https://openalex.org/W2168429115","doi":"https://doi.org/10.1002/cta.4490200310","title":"SMOS: A CAD\u2010compatible statistical model for analogue mos integrated circuit simulation","display_name":"SMOS: A CAD\u2010compatible statistical model for analogue mos integrated circuit simulation","publication_year":1992,"publication_date":"1992-05-01","ids":{"openalex":"https://openalex.org/W2168429115","doi":"https://doi.org/10.1002/cta.4490200310","mag":"2168429115"},"language":"en","primary_location":{"id":"doi:10.1002/cta.4490200310","is_oa":false,"landing_page_url":"https://doi.org/10.1002/cta.4490200310","pdf_url":null,"source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066395747","display_name":"Christopher Michael","orcid":null},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Michael","raw_affiliation_strings":["Solid-State Microelectronics Laboratory, Department of Electrical Engineering, the Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Solid-State Microelectronics Laboratory, Department of Electrical Engineering, the Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272, U.S.A","institution_ids":["https://openalex.org/I52357470"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109587475","display_name":"Christopher J. Abel","orcid":null},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Abel","raw_affiliation_strings":["Solid-State Microelectronics Laboratory, Department of Electrical Engineering, the Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Solid-State Microelectronics Laboratory, Department of Electrical Engineering, the Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272, U.S.A","institution_ids":["https://openalex.org/I52357470"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103567619","display_name":"Mohammed Ismail","orcid":null},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammed Ismail","raw_affiliation_strings":["Solid-State Microelectronics Laboratory, Department of Electrical Engineering, the Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Solid-State Microelectronics Laboratory, Department of Electrical Engineering, the Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272, U.S.A","institution_ids":["https://openalex.org/I52357470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I52357470"],"apc_list":{"value":3660,"currency":"USD","value_usd":3660},"apc_paid":null,"fwci":1.0562,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.78177888,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"20","issue":"3","first_page":"327","last_page":"348"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8281958103179932},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.6592198610305786},{"id":"https://openalex.org/keywords/statistical-model","display_name":"Statistical model","score":0.6007477641105652},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5826659202575684},{"id":"https://openalex.org/keywords/electronic-circuit-simulation","display_name":"Electronic circuit simulation","score":0.5427582263946533},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5296758413314819},{"id":"https://openalex.org/keywords/variance","display_name":"Variance (accounting)","score":0.4869054853916168},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4803774952888489},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.47355714440345764},{"id":"https://openalex.org/keywords/transistor-model","display_name":"Transistor model","score":0.4729713499546051},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46569737792015076},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4474937915802002},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4095648527145386},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.27881792187690735},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.23209354281425476},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20887067914009094},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19309207797050476},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1676081120967865},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1341601312160492}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8281958103179932},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.6592198610305786},{"id":"https://openalex.org/C114289077","wikidata":"https://www.wikidata.org/wiki/Q3284399","display_name":"Statistical model","level":2,"score":0.6007477641105652},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5826659202575684},{"id":"https://openalex.org/C46205389","wikidata":"https://www.wikidata.org/wiki/Q1270401","display_name":"Electronic circuit simulation","level":3,"score":0.5427582263946533},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5296758413314819},{"id":"https://openalex.org/C196083921","wikidata":"https://www.wikidata.org/wiki/Q7915758","display_name":"Variance (accounting)","level":2,"score":0.4869054853916168},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4803774952888489},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.47355714440345764},{"id":"https://openalex.org/C150169584","wikidata":"https://www.wikidata.org/wiki/Q7834319","display_name":"Transistor model","level":4,"score":0.4729713499546051},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46569737792015076},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4474937915802002},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4095648527145386},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27881792187690735},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.23209354281425476},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20887067914009094},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19309207797050476},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1676081120967865},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1341601312160492},{"id":"https://openalex.org/C121955636","wikidata":"https://www.wikidata.org/wiki/Q4116214","display_name":"Accounting","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/cta.4490200310","is_oa":false,"landing_page_url":"https://doi.org/10.1002/cta.4490200310","pdf_url":null,"source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1972687534","https://openalex.org/W1980263616","https://openalex.org/W1982756257","https://openalex.org/W1998168457","https://openalex.org/W2000146887","https://openalex.org/W2001155586","https://openalex.org/W2007569252","https://openalex.org/W2032628911","https://openalex.org/W2035513689","https://openalex.org/W2058853065","https://openalex.org/W2082544129","https://openalex.org/W2110033475","https://openalex.org/W2121702090","https://openalex.org/W2140020998","https://openalex.org/W2140823559","https://openalex.org/W2797734127","https://openalex.org/W6652780124"],"related_works":["https://openalex.org/W2797744477","https://openalex.org/W2018560541","https://openalex.org/W2908026729","https://openalex.org/W1629312120","https://openalex.org/W2134827725","https://openalex.org/W4234364140","https://openalex.org/W2922342296","https://openalex.org/W3023960978","https://openalex.org/W1972185800","https://openalex.org/W3118612961"],"abstract_inverted_index":{"Abstract":[0],"An":[1],"analogue":[2,119],"CAD":[3],"tool":[4,28],"capable":[5],"of":[6,26,42,55,97,116],"simulating":[7],"MOS":[8,33],"circuit":[9,45,103],"performance":[10,91],"variance":[11],"caused":[12],"by":[13,74,94],"intra\u2010die":[14],"variability":[15],"inherent":[16],"to":[17,62],"IC":[18],"fabrication":[19],"processes":[20],"has":[21],"been":[22],"developed.":[23],"the":[24,40,56,65,69,75,78,98,121,125],"nucleus":[25],"this":[27],"is":[29,60,81],"a":[30],"general,":[31],"CAD\u2010compatible,":[32],"statistical":[34,76,79,99],"model":[35,57,80,100],"called":[36],"SMOS":[37],"which":[38,86],"comprehends":[39],"effects":[41],"device":[43],"geometry,":[44],"layout":[46],"and":[47,68,107,114,124],"transistor":[48],"bias":[49],"on":[50],"parameter":[51],"variance.":[52],"an":[53],"example":[54],"calculation":[58],"procedure":[59],"presented":[61],"illustrate":[63],"both":[64],"modelling":[66],"algorithms":[67],"process":[70],"characterization":[71],"data":[72,85],"required":[73],"model.":[77],"verified":[82],"through":[83],"experimental":[84],"show":[87],"excellent":[88],"agreement":[89],"with":[90],"variances":[92],"predicted":[93],"simulation.":[95],"Implementations":[96],"in":[101],"two":[102,117],"simulation":[104,115],"environments,":[105],"SPICE":[106],"APLAC,":[108],"are":[109,128],"also":[110],"described.":[111],"Statistical":[112],"analysis":[113],"basic":[118],"subcircuits,":[120],"current":[122],"mirror":[123],"source\u2010coupled":[126],"pair,":[127],"presented.":[129]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}