{"id":"https://openalex.org/W3185557006","doi":"https://doi.org/10.1002/cta.3109","title":"A scalable high\u2010speed hybrid 1\u2010bit full adder design using XOR\u2010XNOR module","display_name":"A scalable high\u2010speed hybrid 1\u2010bit full adder design using XOR\u2010XNOR module","publication_year":2021,"publication_date":"2021-07-22","ids":{"openalex":"https://openalex.org/W3185557006","doi":"https://doi.org/10.1002/cta.3109","mag":"3185557006"},"language":"en","primary_location":{"id":"doi:10.1002/cta.3109","is_oa":false,"landing_page_url":"https://doi.org/10.1002/cta.3109","pdf_url":null,"source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100754616","display_name":"Mehedi Hasan","orcid":"https://orcid.org/0000-0002-5767-6728"},"institutions":[{"id":"https://openalex.org/I157386601","display_name":"North South University","ror":"https://ror.org/05wdbfp45","country_code":"BD","type":"education","lineage":["https://openalex.org/I157386601"]},{"id":"https://openalex.org/I91090688","display_name":"University of Science and Technology Chittagong","ror":"https://ror.org/00w9tx359","country_code":"BD","type":"education","lineage":["https://openalex.org/I91090688"]}],"countries":["BD"],"is_corresponding":true,"raw_author_name":"Mehedi Hasan","raw_affiliation_strings":["Department of Electrical and Computer Engineering North South University  Dhaka Bangladesh","Department of Electrical and Electronic Engineering University of Science and Technology Chittagong  Chattogram Bangladesh","Department of Electrical and Computer Engineering, North South University, Dhaka, Bangladesh","Department of Electrical and Electronic Engineering, University of Science and Technology Chittagong, Chattogram, Bangladesh"],"raw_orcid":"https://orcid.org/0000-0002-5767-6728","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering North South University  Dhaka Bangladesh","institution_ids":["https://openalex.org/I157386601"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering University of Science and Technology Chittagong  Chattogram Bangladesh","institution_ids":["https://openalex.org/I91090688"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North South University, Dhaka, Bangladesh","institution_ids":["https://openalex.org/I157386601"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Science and Technology Chittagong, Chattogram, Bangladesh","institution_ids":["https://openalex.org/I91090688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016818384","display_name":"Sharnali Islam","orcid":"https://orcid.org/0000-0002-0218-7337"},"institutions":[{"id":"https://openalex.org/I205746353","display_name":"University of Dhaka","ror":"https://ror.org/05wv2vq37","country_code":"BD","type":"education","lineage":["https://openalex.org/I205746353"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Sharnali Islam","raw_affiliation_strings":["Department of Electrical and Electronic Engineering University of Dhaka  Dhaka Bangladesh","Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering University of Dhaka  Dhaka Bangladesh","institution_ids":["https://openalex.org/I205746353"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh","institution_ids":["https://openalex.org/I205746353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073527864","display_name":"Mainul Hossain","orcid":"https://orcid.org/0000-0001-9011-9029"},"institutions":[{"id":"https://openalex.org/I205746353","display_name":"University of Dhaka","ror":"https://ror.org/05wv2vq37","country_code":"BD","type":"education","lineage":["https://openalex.org/I205746353"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Mainul Hossain","raw_affiliation_strings":["Department of Electrical and Electronic Engineering University of Dhaka  Dhaka Bangladesh","Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering University of Dhaka  Dhaka Bangladesh","institution_ids":["https://openalex.org/I205746353"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh","institution_ids":["https://openalex.org/I205746353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023073914","display_name":"Hasan U. Zaman","orcid":"https://orcid.org/0000-0002-8146-6894"},"institutions":[{"id":"https://openalex.org/I157386601","display_name":"North South University","ror":"https://ror.org/05wdbfp45","country_code":"BD","type":"education","lineage":["https://openalex.org/I157386601"]},{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]},{"id":"https://openalex.org/I4210101778","display_name":"Samsung (United States)","ror":"https://ror.org/01bfbvm65","country_code":"US","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210101778"]}],"countries":["BD","KR","US"],"is_corresponding":false,"raw_author_name":"Hasan U. Zaman","raw_affiliation_strings":["Department of Electrical and Computer Engineering North South University  Dhaka Bangladesh","Samsung Austin R&amp;D Center Samsung Corporation  Austin Texas USA","Department of Electrical and Computer Engineering, North South University, Dhaka, Bangladesh","Samsung Austin R&D Center, Samsung Corporation, Austin, Texas, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering North South University  Dhaka Bangladesh","institution_ids":["https://openalex.org/I157386601"]},{"raw_affiliation_string":"Samsung Austin R&amp;D Center Samsung Corporation  Austin Texas USA","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North South University, Dhaka, Bangladesh","institution_ids":["https://openalex.org/I157386601"]},{"raw_affiliation_string":"Samsung Austin R&D Center, Samsung Corporation, Austin, Texas, USA","institution_ids":["https://openalex.org/I4210101778"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100754616"],"corresponding_institution_ids":["https://openalex.org/I157386601","https://openalex.org/I91090688"],"apc_list":{"value":3660,"currency":"USD","value_usd":3660},"apc_paid":null,"fwci":1.1257,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.75835482,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"49","issue":"11","first_page":"3597","last_page":"3606"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.9630024433135986},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8703888654708862},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6291802525520325},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.6009849309921265},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.5282289981842041},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.514381468296051},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4666317403316498},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4597253203392029},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43285736441612244},{"id":"https://openalex.org/keywords/4-bit","display_name":"4-bit","score":0.41231846809387207},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3853365182876587},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.24203798174858093},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19932624697685242},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1856277883052826},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1679697036743164}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.9630024433135986},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8703888654708862},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6291802525520325},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.6009849309921265},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.5282289981842041},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.514381468296051},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4666317403316498},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4597253203392029},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43285736441612244},{"id":"https://openalex.org/C194986542","wikidata":"https://www.wikidata.org/wiki/Q229932","display_name":"4-bit","level":3,"score":0.41231846809387207},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3853365182876587},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.24203798174858093},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19932624697685242},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1856277883052826},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1679697036743164}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/cta.3109","is_oa":false,"landing_page_url":"https://doi.org/10.1002/cta.3109","pdf_url":null,"source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1597709992","https://openalex.org/W2007109372","https://openalex.org/W2046103068","https://openalex.org/W2073828402","https://openalex.org/W2088095580","https://openalex.org/W2097193789","https://openalex.org/W2141849037","https://openalex.org/W2144038159","https://openalex.org/W2157555699","https://openalex.org/W2159229333","https://openalex.org/W2187874179","https://openalex.org/W2512305791","https://openalex.org/W2530873177","https://openalex.org/W2791867184","https://openalex.org/W2899979858","https://openalex.org/W2910594020","https://openalex.org/W2913719236","https://openalex.org/W2914348382","https://openalex.org/W2922420481","https://openalex.org/W2960348933","https://openalex.org/W2966167417","https://openalex.org/W2972696482","https://openalex.org/W2998002330","https://openalex.org/W3034899143","https://openalex.org/W3162163331","https://openalex.org/W3165365636","https://openalex.org/W3212045078"],"related_works":["https://openalex.org/W3093482235","https://openalex.org/W4205386189","https://openalex.org/W2950842282","https://openalex.org/W2527584300","https://openalex.org/W2555468383","https://openalex.org/W3166220017","https://openalex.org/W2610514210","https://openalex.org/W2333351870","https://openalex.org/W2395826134","https://openalex.org/W2620958856"],"abstract_inverted_index":{"Abstract":[0],"High\u2010speed":[1],"XOR\u2010XNOR\u2010based":[2,99,123],"hybrid":[3,124],"full":[4],"adder":[5,66,109,118],"(FA)":[6],"using":[7],"a":[8,107,129],"combination":[9],"of":[10,32,51,140],"three":[11],"logic":[12],"techniques":[13],"(transmission":[14],"gate":[15],"[TG],":[16],"conventional":[17],"CMOS":[18],"[CCMOS],":[19],"pass":[20],"transistor":[21],"[PT])":[22],"is":[23],"presented":[24,36],"in":[25,37,63,93,114,136],"this":[26,38],"work.":[27],"Performance":[28],"analysis":[29],"and":[30,78],"validation":[31],"the":[33,52,79,94,121,133],"FA":[34,59,81,100,125],"design":[35,53],"work":[39],"have":[40],"been":[41,55,71],"realized":[42],"with":[43],"reference":[44],"to":[45,61,86,132],"10":[46],"state\u2010of\u2010the\u2010art":[47],"FAs.":[48],"The":[49,97],"scalability":[50],"has":[54,70],"tested":[56],"by":[57],"extending":[58],"up":[60,85],"32\u2010bits":[62,87],"ripple":[64],"carry":[65],"(RCA)":[67],"style.":[68],"It":[69],"observed":[72],"that":[73],"only":[74],"four":[75],"existing":[76,134],"FAs":[77,135],"proposed":[80,98,122],"could":[82],"be":[83],"scaled":[84],"without":[88],"including":[89],"voltage":[90],"restoration":[91],"buffers":[92],"internal":[95],"stages.":[96],"showed":[101],"excellent":[102],"performance":[103],"metrics,":[104],"both":[105],"as":[106,111,113,128],"1\u2010bit":[108],"cell":[110],"well":[112],"wide":[115],"word":[116],"length":[117],"form.":[119],"Hence,":[120],"can":[126],"serve":[127],"better":[130],"alternative":[131],"digital":[137],"arithmetic":[138],"blocks":[139],"modern":[141],"microprocessors.":[142]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2025-10-10T00:00:00"}
