{"id":"https://openalex.org/W1727049600","doi":"https://doi.org/10.1002/9780470050118.ecse312","title":"<scp>VLSI</scp>Circuit Layout","display_name":"<scp>VLSI</scp>Circuit Layout","publication_year":2008,"publication_date":"2008-09-11","ids":{"openalex":"https://openalex.org/W1727049600","doi":"https://doi.org/10.1002/9780470050118.ecse312","mag":"1727049600"},"language":"en","primary_location":{"id":"doi:10.1002/9780470050118.ecse312","is_oa":false,"landing_page_url":"https://doi.org/10.1002/9780470050118.ecse312","pdf_url":null,"source":{"id":"https://openalex.org/S4306534807","display_name":"Wiley Encyclopedia of Computer Science and Engineering","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Wiley Encyclopedia of Computer Science and Engineering","raw_type":"other"},"type":"other","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100705837","display_name":"Lihong Zhang","orcid":"https://orcid.org/0000-0003-2946-8072"},"institutions":[{"id":"https://openalex.org/I130438778","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03","country_code":"CA","type":"education","lineage":["https://openalex.org/I130438778"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Lihong Zhang","raw_affiliation_strings":["Memorial University of Newfoundland, St. John's, Newfoundland, Canada","Memorial University of Newfoundland St. John's, Newfoundland Canada"],"affiliations":[{"raw_affiliation_string":"Memorial University of Newfoundland, St. John's, Newfoundland, Canada","institution_ids":["https://openalex.org/I130438778"]},{"raw_affiliation_string":"Memorial University of Newfoundland St. John's, Newfoundland Canada","institution_ids":["https://openalex.org/I130438778"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5100705837"],"corresponding_institution_ids":["https://openalex.org/I130438778"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.9388728737831116},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8048303127288818},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.7700256109237671},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6610148549079895},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6358612775802612},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5207110047340393},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4789220094680786},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3963729739189148},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3887118399143219},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3508656620979309},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25718915462493896},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24812939763069153}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.9388728737831116},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8048303127288818},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.7700256109237671},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6610148549079895},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6358612775802612},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5207110047340393},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4789220094680786},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3963729739189148},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3887118399143219},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3508656620979309},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25718915462493896},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24812939763069153},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/9780470050118.ecse312","is_oa":false,"landing_page_url":"https://doi.org/10.1002/9780470050118.ecse312","pdf_url":null,"source":{"id":"https://openalex.org/S4306534807","display_name":"Wiley Encyclopedia of Computer Science and Engineering","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Wiley Encyclopedia of Computer Science and Engineering","raw_type":"other"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7400000095367432,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W560265616","https://openalex.org/W1555778358","https://openalex.org/W1568614804","https://openalex.org/W1984283136","https://openalex.org/W1991479057","https://openalex.org/W1993614657","https://openalex.org/W1996746141","https://openalex.org/W2002886574","https://openalex.org/W2072027869","https://openalex.org/W2102676394","https://openalex.org/W2107668615","https://openalex.org/W2118049690","https://openalex.org/W2125531773","https://openalex.org/W2133492470","https://openalex.org/W2141776905","https://openalex.org/W2149029467","https://openalex.org/W2161455936","https://openalex.org/W3141650728","https://openalex.org/W4205355374","https://openalex.org/W4230223219","https://openalex.org/W4246161403","https://openalex.org/W4246306476","https://openalex.org/W4256007160","https://openalex.org/W4300809515"],"related_works":["https://openalex.org/W2133901311","https://openalex.org/W2136768364","https://openalex.org/W2087871358","https://openalex.org/W2120361800","https://openalex.org/W2182445672","https://openalex.org/W4386643835","https://openalex.org/W2781601456","https://openalex.org/W3010631755","https://openalex.org/W2181385951","https://openalex.org/W2783276420"],"abstract_inverted_index":{"Abstract":[0],"VLSI":[1,18,47,115],"circuits":[2,101],"have":[3],"experienced":[4],"significant":[5],"growth":[6],"in":[7,68],"the":[8,31,40,77,93,113],"past":[9],"half":[10],"a":[11,89],"century.":[12],"As":[13],"an":[14,22],"important":[15],"design":[16,20,36,43,57,97],"phase,":[17],"physical":[19,35,42,56,96],"is":[21,50],"extremely":[23],"tedious":[24],"and":[25,62,64,76],"error\u2010prone":[26],"process.":[27],"In":[28,52],"this":[29],"article,":[30],"fundamental":[32],"characteristics":[33],"of":[34,73,95],"are":[37,66,80,85,102],"described.":[38],"Then":[39],"general":[41,91],"methodology":[44],"mainly":[45],"for":[46,98],"digital":[48],"systems":[49],"discussed.":[51],"particular,":[53],"three":[54],"major":[55],"subproblems,":[58],"including":[59],"partitioning,":[60],"floorplan":[61],"placement,":[63],"routing,":[65],"explained":[67],"more":[69,90],"detail.":[70],"The":[71,82,105],"formulation":[72],"each":[74],"subproblem":[75],"related":[78],"algorithms":[79],"presented.":[81],"state\u2010of\u2010the\u2010art":[83],"teachniques":[84],"summarized.":[86],"To":[87],"exhibit":[88],"overview,":[92],"features":[94],"analog":[99],"integrated":[100],"also":[103],"outlined.":[104],"article":[106],"concludes":[107],"with":[108],"some":[109],"emerging":[110],"topics":[111],"regarding":[112],"modern":[114],"layout.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2}],"updated_date":"2026-02-20T08:17:22.645390","created_date":"2025-10-10T00:00:00"}
