{"id":"https://openalex.org/W2049386500","doi":"https://doi.org/10.1002/1096-9128(20000810)12:9<799::aid-cpe476>3.0.co;2-1","title":"Shared-memory communication approaches for an MPI message-passing library","display_name":"Shared-memory communication approaches for an MPI message-passing library","publication_year":2000,"publication_date":"2000-01-01","ids":{"openalex":"https://openalex.org/W2049386500","doi":"https://doi.org/10.1002/1096-9128(20000810)12:9<799::aid-cpe476>3.0.co;2-1","mag":"2049386500"},"language":"en","primary_location":{"id":"doi:10.1002/1096-9128(20000810)12:9<799::aid-cpe476>3.0.co;2-1","is_oa":false,"landing_page_url":"https://doi.org/10.1002/1096-9128(20000810)12:9<799::aid-cpe476>3.0.co;2-1","pdf_url":null,"source":{"id":"https://openalex.org/S4210209928","display_name":"Concurrency Practice and Experience","issn_l":"1040-3108","issn":["1040-3108","1096-9128"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Concurrency: Practice and Experience","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035037811","display_name":"Boris V. Protopopov","orcid":null},"institutions":[{"id":"https://openalex.org/I99041443","display_name":"Mississippi State University","ror":"https://ror.org/0432jq872","country_code":"US","type":"education","lineage":["https://openalex.org/I4210141039","https://openalex.org/I99041443"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Boris V. Protopopov","raw_affiliation_strings":["Department of Computer Science and NSF Engineering Research Center, Mississippi State University, P.O. Box 9637, Mississippi State, MS 39762, U.S.A"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and NSF Engineering Research Center, Mississippi State University, P.O. Box 9637, Mississippi State, MS 39762, U.S.A","institution_ids":["https://openalex.org/I99041443"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026440046","display_name":"Anthony Skjellum","orcid":"https://orcid.org/0000-0001-5252-6600"},"institutions":[{"id":"https://openalex.org/I99041443","display_name":"Mississippi State University","ror":"https://ror.org/0432jq872","country_code":"US","type":"education","lineage":["https://openalex.org/I4210141039","https://openalex.org/I99041443"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Anthony Skjellum","raw_affiliation_strings":["Department of Computer Science and NSF Engineering Research Center, Mississippi State University, P.O. Box 9637, Mississippi State, MS 39762, U.S.A"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and NSF Engineering Research Center, Mississippi State University, P.O. Box 9637, Mississippi State, MS 39762, U.S.A","institution_ids":["https://openalex.org/I99041443"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5026440046"],"corresponding_institution_ids":["https://openalex.org/I99041443"],"apc_list":null,"apc_paid":null,"fwci":0.3042,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.63248271,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"12","issue":"9","first_page":"799","last_page":"820"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8758913278579712},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.8024919033050537},{"id":"https://openalex.org/keywords/message-passing","display_name":"Message passing","score":0.6480364203453064},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.6181818246841431},{"id":"https://openalex.org/keywords/message-passing-interface","display_name":"Message Passing Interface","score":0.5862716436386108},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.5206643342971802},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.46374472975730896},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45466840267181396},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44456925988197327},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33799582719802856},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.30433475971221924},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.2949603497982025},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2501843571662903},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.12341967225074768}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8758913278579712},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.8024919033050537},{"id":"https://openalex.org/C854659","wikidata":"https://www.wikidata.org/wiki/Q1859284","display_name":"Message passing","level":2,"score":0.6480364203453064},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.6181818246841431},{"id":"https://openalex.org/C166782233","wikidata":"https://www.wikidata.org/wiki/Q127879","display_name":"Message Passing Interface","level":3,"score":0.5862716436386108},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.5206643342971802},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.46374472975730896},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45466840267181396},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44456925988197327},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33799582719802856},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.30433475971221924},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.2949603497982025},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2501843571662903},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.12341967225074768},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/1096-9128(20000810)12:9<799::aid-cpe476>3.0.co;2-1","is_oa":false,"landing_page_url":"https://doi.org/10.1002/1096-9128(20000810)12:9<799::aid-cpe476>3.0.co;2-1","pdf_url":null,"source":{"id":"https://openalex.org/S4210209928","display_name":"Concurrency Practice and Experience","issn_l":"1040-3108","issn":["1040-3108","1096-9128"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Concurrency: Practice and Experience","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1579133219","https://openalex.org/W2005897603","https://openalex.org/W2053585840","https://openalex.org/W2081612620","https://openalex.org/W2166071597","https://openalex.org/W2168413153","https://openalex.org/W4210348154","https://openalex.org/W4235077482","https://openalex.org/W6606192497","https://openalex.org/W6680059641","https://openalex.org/W6737467347"],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W2353146130","https://openalex.org/W2154020360","https://openalex.org/W2498758832","https://openalex.org/W1824582190","https://openalex.org/W254684032","https://openalex.org/W2080451007","https://openalex.org/W1848192231","https://openalex.org/W4291801887","https://openalex.org/W120214571"],"abstract_inverted_index":{"This":[0],"paper":[1,73],"discusses":[2],"several":[3],"approaches":[4],"to":[5,98],"designing":[6],"and":[7,37,54,90,124],"implementing":[8],"shared-memory":[9,33,50,83,117],"communication":[10,35,84,112],"protocol":[11],"modules":[12],"for":[13,29,32,52,82,136],"the":[14,45,56,77,80,94,105,126],"message-passing":[15],"interface":[16],"(MPI)":[17],"libraries,":[18],"colloquially":[19],"called":[20],"\u2018shared-memory":[21],"devices\u2019.":[22],"The":[23,59,69],"authors":[24,46,60,78],"present":[25,62,79],"a":[26,141],"new":[27],"taxonomy":[28,81,103],"classifying":[30],"designs":[31],"MPI":[34,144],"devices":[36,51,95],"formulate":[38],"design":[39,107],"evaluation":[40],"criteria.":[41,108],"Using":[42],"these":[43,130],"criteria,":[44],"compare":[47],"three":[48],"existing":[49,115],"MPICH":[53,116,133],"choose":[55],"best":[57],"one.":[58],"also":[61],"experimental":[63],"results":[64],"that":[65,96,129],"support":[66],"their":[67,102,122],"choice.":[68],"contributions":[70],"of":[71,93,101,114,121],"this":[72],"are":[74],"three-fold.":[75],"First,":[76],"devices.":[85],"Second,":[86],"they":[87,110],"show":[88,125],"advantages":[89],"potential":[91],"problems":[92],"belong":[97],"different":[99],"classes":[100],"using":[104],"formulated":[106],"Third,":[109],"analyze":[111],"performance":[113,127],"devices,":[118],"discuss":[119],"optimizations":[120,131],"performance,":[123],"gains":[128],"yield.":[132],"is":[134,140],"used":[135,143],"comparison,":[137],"since":[138],"it":[139],"widely":[142],"implementation.":[145],"Copyright":[146],"\u00a9":[147],"2000":[148],"John":[149],"Wiley":[150],"&":[151],"Sons,":[152],"Ltd.":[153]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}