{"id":"https://openalex.org/W2082630917","doi":"https://doi.org/10.1002/(sici)1520-684x(199804)29:4<70::aid-scj7>3.0.co;2-l","title":"Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images","display_name":"Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images","publication_year":1998,"publication_date":"1998-04-01","ids":{"openalex":"https://openalex.org/W2082630917","doi":"https://doi.org/10.1002/(sici)1520-684x(199804)29:4<70::aid-scj7>3.0.co;2-l","mag":"2082630917"},"language":"en","primary_location":{"id":"doi:10.1002/(sici)1520-684x(199804)29:4<70::aid-scj7>3.0.co;2-l","is_oa":false,"landing_page_url":"https://doi.org/10.1002/(sici)1520-684x(199804)29:4<70::aid-scj7>3.0.co;2-l","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041722144","display_name":"Koji Nakamae","orcid":"https://orcid.org/0000-0001-9269-3868"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Koji Nakamae","raw_affiliation_strings":["Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565"],"affiliations":[{"raw_affiliation_string":"Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101897882","display_name":"Shinji Yokoyama","orcid":"https://orcid.org/0000-0003-0552-9168"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinji Yokoyama","raw_affiliation_strings":["Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565"],"affiliations":[{"raw_affiliation_string":"Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074393862","display_name":"Atsushi Onishi","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Onishi","raw_affiliation_strings":["Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565"],"affiliations":[{"raw_affiliation_string":"Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026665036","display_name":"Hiromu Fujioka","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiromu Fujioka","raw_affiliation_strings":["Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565"],"affiliations":[{"raw_affiliation_string":"Department of Information Systems Engineering, Faculty of Engineering, Osaka University, Osaka, Japan 565","institution_ids":["https://openalex.org/I98285908"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5041722144"],"corresponding_institution_ids":["https://openalex.org/I98285908"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.29948885,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"29","issue":"4","first_page":"70","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13114","display_name":"Image Processing Techniques and Applications","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13114","display_name":"Image Processing Techniques and Applications","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12111","display_name":"Industrial Vision Systems and Defect Detection","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/polygon","display_name":"Polygon (computer graphics)","score":0.7622015476226807},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7035037279129028},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7021462321281433},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6393867135047913},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6336345672607422},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5833433866500854},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.484782874584198},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.45200014114379883},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4427647292613983},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3747931718826294},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3345363736152649},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23572465777397156},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.20011308789253235},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15489324927330017},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09491804242134094}],"concepts":[{"id":"https://openalex.org/C190694206","wikidata":"https://www.wikidata.org/wiki/Q3276654","display_name":"Polygon (computer graphics)","level":3,"score":0.7622015476226807},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7035037279129028},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7021462321281433},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6393867135047913},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6336345672607422},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5833433866500854},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.484782874584198},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.45200014114379883},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4427647292613983},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3747931718826294},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3345363736152649},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23572465777397156},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.20011308789253235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15489324927330017},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09491804242134094},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/(sici)1520-684x(199804)29:4<70::aid-scj7>3.0.co;2-l","is_oa":false,"landing_page_url":"https://doi.org/10.1002/(sici)1520-684x(199804)29:4<70::aid-scj7>3.0.co;2-l","pdf_url":null,"source":{"id":"https://openalex.org/S58208175","display_name":"Systems and Computers in Japan","issn_l":"0882-1666","issn":["0882-1666","1520-684X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Systems and Computers in Japan","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1980208071","https://openalex.org/W2567436235"],"related_works":["https://openalex.org/W2155019192","https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2072989701","https://openalex.org/W1738647919","https://openalex.org/W3000179092","https://openalex.org/W1986774039","https://openalex.org/W2050511294","https://openalex.org/W2118321428"],"abstract_inverted_index":{"For":[0],"the":[1,12,29,68,73,95,101,106,113,129,145,150,167,172,177,182,189,197],"purpose":[2],"of":[3,14,45,83,115,118,128,138,169,171,201,206],"constructing":[4],"a":[5,20,35,54,58,84,87,91,98,116,125,136,156,207],"fault":[6],"diagnosis":[7],"assistance":[8],"system":[9,23,52,203],"based":[10],"on":[11,161],"concept":[13],"so-called":[15],"\u201creverse":[16],"engineering,\u201d":[17],"we":[18,154,185],"propose":[19],"circuit":[21,55],"recognition":[22],"for":[24],"CMOS":[25,37,208],"circuits":[26],"designed":[27,41],"with":[28,34],"standard-cell":[30,40,69],"design":[31],"and":[32,48,72,90,149,181,192],"manufactured":[33],"two-level-metal-layer":[36],"process.":[38],"The":[39,51,79,164,216],"layout":[42,70,102],"is":[43,62,110,132],"composed":[44],"cell":[46,85,190],"arrays":[47],"routing":[49,198],"channels.":[50],"recognizes":[53],"by":[56],"using":[57],"knowledge":[59,80,183],"base":[60,81],"that":[61],"built":[63],"from":[64,124],"features":[65],"included":[66],"in":[67,100,105,188,196],"data":[71,103],"observed":[74,130,173],"optical":[75,210],"microscope":[76,211],"interconnection":[77,121,148,174,179],"patterns.":[78],"consists":[82],"library,":[86,89,97],"polygon":[88,96,99],"rule":[92],"base.":[93],"In":[94,140],"described":[104,134],"GDS":[107],"II":[108],"format":[109],"changed":[111],"into":[112],"description":[114],"set":[117,137],"rectangles.":[119,139],"An":[120],"pattern":[122],"extracted":[123,178],"binary":[126],"version":[127],"image":[131,212],"also":[133],"as":[135],"order":[141],"to":[142,204],"distinguish":[143],"between":[144,194],"1st-layer":[146],"A1":[147,152],"2nd-layer":[151],"interconnection,":[153],"introduce":[155],"parameter":[157,165],"called":[158],"\u201cedge":[159],"strength\u201d":[160],"each":[162],"rectangle.":[163],"indicates":[166],"degree":[168],"sharpness":[170],"edge.":[175],"From":[176],"patterns":[180],"base,":[184],"recognize":[186],"cells":[187,195],"array":[191],"connections":[193],"channel.":[199],"Application":[200],"this":[202],"part":[205],"VLSI":[209],"showed":[213],"its":[214],"validity.":[215],"total":[217],"processing":[218],"time":[219],"was":[220],"306":[221],"s.":[222],"\u00a9":[223],"1998":[224,232],"Scripta":[225],"Technica,":[226],"Syst":[227],"Comp":[228],"Jpn,":[229],"29(4):":[230],"70\u201378,":[231]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
