{"id":"https://openalex.org/W2054506383","doi":"https://doi.org/10.1002/(sici)1096-9128(199606)8:5<387::aid-cpe223>3.0.co;2-i","title":"Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture","display_name":"Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture","publication_year":1996,"publication_date":"1996-06-01","ids":{"openalex":"https://openalex.org/W2054506383","doi":"https://doi.org/10.1002/(sici)1096-9128(199606)8:5<387::aid-cpe223>3.0.co;2-i","mag":"2054506383"},"language":"en","primary_location":{"id":"doi:10.1002/(sici)1096-9128(199606)8:5<387::aid-cpe223>3.0.co;2-i","is_oa":false,"landing_page_url":"https://doi.org/10.1002/(sici)1096-9128(199606)8:5<387::aid-cpe223>3.0.co;2-i","pdf_url":null,"source":{"id":"https://openalex.org/S4210209928","display_name":"Concurrency Practice and Experience","issn_l":"1040-3108","issn":["1040-3108","1096-9128"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Concurrency: Practice and Experience","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100407758","display_name":"Xi Li","orcid":"https://orcid.org/0000-0003-3023-1662"},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xi Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, 07102, USA","Department of Electrical and Computer Engineering, New Jersey Institute of Tech, Newark, New Jersey 07102, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, 07102, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Tech, Newark, New Jersey 07102, USA","institution_ids":["https://openalex.org/I118118575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076762145","display_name":"Sotirios G. Ziavras","orcid":"https://orcid.org/0000-0002-3764-1528"},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sotirios G. Ziavras","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, 07102, USA","Department of Electrical and Computer Engineering, New Jersey Institute of Tech, Newark, New Jersey 07102, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, 07102, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Tech, Newark, New Jersey 07102, USA","institution_ids":["https://openalex.org/I118118575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087932443","display_name":"C.N. Manikopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Constantine N. Manikopoulos","raw_affiliation_strings":["Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, 07102, USA","Department of Electrical and Computer Engineering, New Jersey Institute of Tech, Newark, New Jersey 07102, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, 07102, USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, New Jersey Institute of Tech, Newark, New Jersey 07102, USA","institution_ids":["https://openalex.org/I118118575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100407758"],"corresponding_institution_ids":["https://openalex.org/I118118575"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.14779532,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"8","issue":"5","first_page":"387","last_page":"411"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8475966453552246},{"id":"https://openalex.org/keywords/message-passing","display_name":"Message passing","score":0.7486797571182251},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7015571594238281},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.662915825843811},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5866516828536987},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5548819899559021},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5479016304016113},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4420829713344574},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.4222663938999176},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23841145634651184}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8475966453552246},{"id":"https://openalex.org/C854659","wikidata":"https://www.wikidata.org/wiki/Q1859284","display_name":"Message passing","level":2,"score":0.7486797571182251},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7015571594238281},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.662915825843811},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5866516828536987},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5548819899559021},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5479016304016113},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4420829713344574},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.4222663938999176},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23841145634651184},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/(sici)1096-9128(199606)8:5<387::aid-cpe223>3.0.co;2-i","is_oa":false,"landing_page_url":"https://doi.org/10.1002/(sici)1096-9128(199606)8:5<387::aid-cpe223>3.0.co;2-i","pdf_url":null,"source":{"id":"https://openalex.org/S4210209928","display_name":"Concurrency Practice and Experience","issn_l":"1040-3108","issn":["1040-3108","1096-9128"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Concurrency: Practice and Experience","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4243844743","https://openalex.org/W3208184694","https://openalex.org/W2498758832","https://openalex.org/W4233541614","https://openalex.org/W1578042825","https://openalex.org/W3163622116","https://openalex.org/W2146401083","https://openalex.org/W4287181807","https://openalex.org/W2366325093","https://openalex.org/W1998761481"],"abstract_inverted_index":{"The":[0,31,42],"paper":[1],"presents":[2],"several":[3],"parallel":[4,63],"DSP":[5],"(digital":[6],"signal":[7],"processing)":[8],"algorithms":[9,43],"and":[10,18],"their":[11],"performance":[12,76],"analysis,":[13],"targetting":[14],"a":[15,57],"hybrid":[16,71],"message-passing":[17,50],"shared-memory":[19,52],"architecture":[20,72],"that":[21,68],"has":[22],"been":[23],"built":[24],"at":[25],"New":[26],"Jersey":[27],"Institute":[28],"of":[29,34,59,61,79],"Technology.":[30],"current":[32],"version":[33],"our":[35,47],"system":[36,48],"contains":[37],"eight":[38],"powerful":[39],"TMS320C40":[40],"processors.":[41],"are":[44],"implemented":[45],"on":[46],"using":[49],"only,":[51,53],"and,":[54],"if":[55],"possible,":[56],"combination":[58],"both":[60],"these":[62],"processing":[64],"paradigms.":[65],"Comparisons":[66],"show":[67],"TurboNet's":[69],"robust,":[70],"results":[73],"in":[74],"significant":[75],"gains":[77],"because":[78],"the":[80],"flexibility":[81],"it":[82],"introduces.":[83]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}