{"id":"https://openalex.org/W98342326","doi":null,"title":"Programmability and Efficiency in Reconfigurable Computer Systems","display_name":"Programmability and Efficiency in Reconfigurable Computer Systems","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W98342326","mag":"98342326"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.79.9704","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.79.9704","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.ucr.edu/~najjar/papers/2003/SA-C-VHDL.pdf","raw_type":"text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112813395","display_name":"Zhi Rui Guo","orcid":"https://orcid.org/0000-0001-5469-4309","observed_orcids":["https://orcid.org/0000-0001-5469-4309"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhi Guo","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0001-5469-4309","affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111603291","display_name":"Dinesh C. Suresh","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dinesh C. Suresh","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5033921328","display_name":"Walid A. Najjar","orcid":"https://orcid.org/0000-0001-6761-6801","observed_orcids":["https://orcid.org/0000-0001-6761-6801"]},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Walid Najjar","raw_affiliation_strings":["University of California, Riverside"],"raw_orcid":"https://orcid.org/0000-0001-6761-6801","affiliations":[{"raw_affiliation_string":"University of California, Riverside","institution_ids":["https://openalex.org/I103635307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4219,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.71811377,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"reconfigurable computing","score":0.9909999966621399},{"id":"https://openalex.org/keywords/high-level-programming-languages","display_name":"high-level programming languages","score":0.671999990940094},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.9980000257492065},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.6959999799728394},{"id":"https://openalex.org/keywords/execution-speed","display_name":"execution speed","score":0.47699999809265137},{"id":"https://openalex.org/keywords/benchmark-comparison","display_name":"benchmark comparison","score":0.4009999930858612}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8191933631896973},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7942692041397095},{"id":"https://openalex.org/C2781039887","wikidata":"https://www.wikidata.org/wiki/Q1391724","display_name":"Factor (programming language)","level":2,"score":0.73971027135849},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.7301867008209229},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5939669609069824},{"id":"https://openalex.org/C115051666","wikidata":"https://www.wikidata.org/wiki/Q6522493","display_name":"Ranging","level":2,"score":0.5593739748001099},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5110632181167603},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5004715919494629},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.47139838337898254},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38104119896888733},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3625025153160095},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.31745603680610657},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07462656497955322},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.79.9704","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.79.9704","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.ucr.edu/~najjar/papers/2003/SA-C-VHDL.pdf","raw_type":"text"},{"id":"mag:98342326","doi":null,"is_oa":false,"landing_page_url":"http://alumni.cs.ucr.edu/~zguo/papers/SA-C-VHDL.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1522086282","https://openalex.org/W1822968287","https://openalex.org/W1944073140","https://openalex.org/W1954746259","https://openalex.org/W2013286553","https://openalex.org/W2048167605","https://openalex.org/W2095968002","https://openalex.org/W2109876904","https://openalex.org/W2112432448","https://openalex.org/W2112928979","https://openalex.org/W2116349307","https://openalex.org/W2166720067"],"related_works":["https://openalex.org/W1993477308","https://openalex.org/W1901327581","https://openalex.org/W2034248530","https://openalex.org/W1522086282","https://openalex.org/W2134053064","https://openalex.org/W1503255010","https://openalex.org/W2096592448","https://openalex.org/W2006428566","https://openalex.org/W1981445285","https://openalex.org/W1997358129"],"abstract_inverted_index":{"It":[0,54],"has":[1],"become":[2],"commonly":[3],"accepted":[4],"that":[5],"higher":[6],"abstraction":[7,25],"programming":[8],"languages":[9],"are":[10],"necessary":[11],"for":[12],"a":[13,29,71,76,86],"wider":[14],"acceptance":[15],"of":[16,45],"reconfigurable":[17],"computing":[18],"technology":[19],"by":[20,75,85],"application":[21],"developers.":[22],"Anytime":[23],"the":[24,42,49,62,66],"level":[26],"is":[27],"increased,":[28],"tradeoff":[30,47],"must":[31],"be":[32],"made":[33],"between":[34],"programmability":[35,84],"and":[36,52],"efficiency.":[37],"This":[38],"paper":[39],"reports":[40],"on":[41,56],"quantitative":[43],"evaluation":[44],"this":[46],"using":[48],"SA-C":[50],"language":[51],"VHDL.":[53],"relies":[55],"four":[57],"benchmark":[58],"codes":[59],"ranging":[60],"from":[61],"trivially":[63],"simple":[64],"to":[65],"complex.":[67],"The":[68],"results":[69],"show":[70],"slowdown":[72],"in":[73,83],"execution":[74],"factor":[77,87],"less":[78],"than":[79],"two":[80],"an":[81],"increase":[82],"as":[88,90],"large":[89],"10.":[91]},"counts_by_year":[],"updated_date":"2026-09-29T14:09:16.559479","created_date":"2016-06-24T00:00:00"}
