{"id":"https://openalex.org/W946658010","doi":"https://doi.org/10.1016/b978-012374123-3.50010-5","title":"Sofware Development Toolchain","display_name":"Sofware Development Toolchain","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W946658010","doi":"https://doi.org/10.1016/b978-012374123-3.50010-5","mag":"946658010"},"language":"en","primary_location":{"id":"doi:10.1016/b978-012374123-3.50010-5","doi":"https://doi.org/10.1016/b978-012374123-3.50010-5","is_oa":false,"landing_page_url":"https://doi.org/10.1016/b978-012374123-3.50010-5","pdf_url":null,"source":{"id":"https://openalex.org/S4306463230","display_name":"Elsevier eBooks","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"ebook platform"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Embedded DSP Processor Design","raw_type":"book-chapter"},"volume":{"id":"https://openalex.org/W4210559432","display_name":"Embedded DSP Processor Design"},"type":"book-chapter","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011014977","display_name":"Dake Liu","orcid":"https://orcid.org/0000-0002-4644-4892","observed_orcids":["https://orcid.org/0000-0002-4644-4892"]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Dake Liu","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5011014977"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"315","last_page":"355"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.0019000000320374966,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0017999999690800905,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/integrated-development-environment","display_name":"integrated development environment","score":0.9549999833106995},{"id":"https://openalex.org/keywords/firmware-development","display_name":"firmware development","score":0.5860000252723694},{"id":"https://openalex.org/keywords/high-level-programming-languages","display_name":"high-level programming languages","score":0.8450000286102295},{"id":"https://openalex.org/keywords/debugging-tools","display_name":"debugging tools","score":0.7870000004768372},{"id":"https://openalex.org/keywords/hardware-design","display_name":"hardware design","score":0.5450000166893005},{"id":"https://openalex.org/keywords/graphical-user-interface","display_name":"graphical user interface","score":0.824999988079071}],"concepts":[{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.9930062294006348},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.2594732642173767},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0815601646900177},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/b978-012374123-3.50010-5","doi":"https://doi.org/10.1016/b978-012374123-3.50010-5","is_oa":false,"landing_page_url":"https://doi.org/10.1016/b978-012374123-3.50010-5","pdf_url":null,"source":{"id":"https://openalex.org/S4306463230","display_name":"Elsevier eBooks","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"ebook platform"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Embedded DSP Processor Design","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W657101550","https://openalex.org/W1583620271","https://openalex.org/W2100644471","https://openalex.org/W2100648544","https://openalex.org/W2109184386","https://openalex.org/W2109507516","https://openalex.org/W6675266387"],"related_works":["https://openalex.org/W2074407913","https://openalex.org/W2785922736","https://openalex.org/W4249420549","https://openalex.org/W3043985871","https://openalex.org/W4299740323","https://openalex.org/W2023330667","https://openalex.org/W2036348404","https://openalex.org/W3161949918","https://openalex.org/W4240033811"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-11-14T11:04:58.165337","created_date":"2016-06-24T00:00:00"}
