{"id":"https://openalex.org/W866528690","doi":null,"title":"New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits","display_name":"New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W866528690","mag":"866528690"},"language":"en","primary_location":{"id":"mag:866528690","doi":null,"is_oa":false,"landing_page_url":"http://www.cqvip.com/QK/71165X/201103/38009150.html","pdf_url":null,"source":{"id":"https://openalex.org/S4306558339","display_name":"\u8ba1\u7b97\u673a\u6280\u672f\u4e0e\u5e94\u7528\uff1a\u82f1\u6587","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"\u8ba1\u7b97\u673a\u6280\u672f\u4e0e\u5e94\u7528\uff1a\u82f1\u6587","raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Subodh Subodh","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Subodh Subodh","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044733140","display_name":"Wairya","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wairya","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030543090","display_name":"Rajendra","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rajendra","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110757897","display_name":"Kumar Kumar","orcid":"https://orcid.org/0000-0001-8287-7495","observed_orcids":["https://orcid.org/0000-0001-8287-7495"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kumar Kumar","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002439716","display_name":"Nagaria","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nagaria","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"Sudarshan","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sudarshan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5110758845","display_name":"Tiwari","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tiwari","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0836,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.78293591,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":"2","issue":"3","first_page":"190","last_page":"198"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0013000000035390258,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0010000000474974513,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/full-adder","display_name":"full adder","score":0.8610000014305115},{"id":"https://openalex.org/keywords/1-bit-adder","display_name":"1-bit adder","score":0.890999972820282},{"id":"https://openalex.org/keywords/cmos-circuits","display_name":"CMOS circuits","score":0.6710000038146973},{"id":"https://openalex.org/keywords/low-voltage-circuits","display_name":"low-voltage circuits","score":0.8100000023841858},{"id":"https://openalex.org/keywords/high-speed-circuits","display_name":"high-speed circuits","score":0.9089999794960022},{"id":"https://openalex.org/keywords/circuit-design-techniques","display_name":"circuit design techniques","score":0.7080000042915344}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8302421569824219},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.66623854637146},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.6096746325492859},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5633045434951782},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5598952770233154},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44972798228263855},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3983237147331238},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3635418713092804},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.265758752822876},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1379954218864441},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:866528690","doi":null,"is_oa":false,"landing_page_url":"http://www.cqvip.com/QK/71165X/201103/38009150.html","pdf_url":null,"source":{"id":"https://openalex.org/S4306558339","display_name":"\u8ba1\u7b97\u673a\u6280\u672f\u4e0e\u5e94\u7528\uff1a\u82f1\u6587","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"\u8ba1\u7b97\u673a\u6280\u672f\u4e0e\u5e94\u7528\uff1a\u82f1\u6587","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2288137816","https://openalex.org/W2328067424","https://openalex.org/W2922900729","https://openalex.org/W2922486914","https://openalex.org/W4415763758","https://openalex.org/W2926425238","https://openalex.org/W2919820294","https://openalex.org/W1861470194","https://openalex.org/W2749208057","https://openalex.org/W7096387875"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-09-29T14:09:16.559479","created_date":"2016-06-24T00:00:00"}
