{"id":"https://openalex.org/W82195920","doi":null,"title":"EFFICIENT MULTIPLIER- LESS VLSI ARCHITECTURES FOR FOLDED PIPELINED COMPLEX FFT CORE 2013","display_name":"EFFICIENT MULTIPLIER- LESS VLSI ARCHITECTURES FOR FOLDED PIPELINED COMPLEX FFT CORE 2013","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W82195920","mag":"82195920"},"language":"en","primary_location":{"id":"mag:82195920","doi":null,"is_oa":false,"landing_page_url":"http://ethesis.nitrkl.ac.in/4911/1/211EC2077.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"dissertation","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113460395","display_name":"Ansuman DiptiSankar Das","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Ansuman DiptiSankar Das","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5113460395"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.000699999975040555,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/complex-fft","display_name":"complex FFT","score":0.7570000290870667},{"id":"https://openalex.org/keywords/multiplier-less-architecture","display_name":"multiplier-less architecture","score":0.753000020980835},{"id":"https://openalex.org/keywords/split-radix-fft","display_name":"split-radix FFT","score":0.7979999780654907},{"id":"https://openalex.org/keywords/radix-4-fft","display_name":"radix-4 FFT","score":0.9750000238418579},{"id":"https://openalex.org/keywords/vlsi-architecture","display_name":"VLSI architecture","score":0.8019999861717224},{"id":"https://openalex.org/keywords/distributed-arithmetic","display_name":"distributed arithmetic","score":0.7900000214576721},{"id":"https://openalex.org/keywords/power-spectrum","display_name":"power spectrum","score":0.8289999961853027},{"id":"https://openalex.org/keywords/compactrio","display_name":"CompactRIO","score":0.8320000171661377},{"id":"https://openalex.org/keywords/labview","display_name":"LabVIEW","score":0.7289999723434448},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.8650000095367432},{"id":"https://openalex.org/keywords/asic-implementation","display_name":"ASIC implementation","score":0.8679999709129333},{"id":"https://openalex.org/keywords/hardware-complexity-reduction","display_name":"hardware complexity reduction","score":0.7519999742507935}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.8992762565612793},{"id":"https://openalex.org/C103755468","wikidata":"https://www.wikidata.org/wiki/Q17103599","display_name":"Split-radix FFT algorithm","level":5,"score":0.6818478107452393},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6480616331100464},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4973285496234894},{"id":"https://openalex.org/C77928272","wikidata":"https://www.wikidata.org/wiki/Q7243214","display_name":"Prime-factor FFT algorithm","level":5,"score":0.4596535563468933},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4271705746650696},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4060801863670349},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38765138387680054},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35463735461235046},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3435462415218353},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1922997236251831},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.07993027567863464},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C166386157","wikidata":"https://www.wikidata.org/wiki/Q1477735","display_name":"Short-time Fourier transform","level":4,"score":0.0},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:82195920","doi":null,"is_oa":false,"landing_page_url":"http://ethesis.nitrkl.ac.in/4911/1/211EC2077.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":51,"referenced_works":["https://openalex.org/W51526084","https://openalex.org/W1501488688","https://openalex.org/W1560989725","https://openalex.org/W1562485189","https://openalex.org/W1625484226","https://openalex.org/W1870590056","https://openalex.org/W1948357167","https://openalex.org/W1970102347","https://openalex.org/W1988893317","https://openalex.org/W1992895834","https://openalex.org/W1993678447","https://openalex.org/W1994520161","https://openalex.org/W2003105206","https://openalex.org/W2025849754","https://openalex.org/W2035137327","https://openalex.org/W2046938074","https://openalex.org/W2047585726","https://openalex.org/W2061171222","https://openalex.org/W2065490696","https://openalex.org/W2074140017","https://openalex.org/W2081072920","https://openalex.org/W2090040267","https://openalex.org/W2095603848","https://openalex.org/W2097780146","https://openalex.org/W2099490452","https://openalex.org/W2100552236","https://openalex.org/W2101767850","https://openalex.org/W2103214047","https://openalex.org/W2103246027","https://openalex.org/W2106805276","https://openalex.org/W2107664197","https://openalex.org/W2108410591","https://openalex.org/W2109829532","https://openalex.org/W2112532950","https://openalex.org/W2119646260","https://openalex.org/W2123119012","https://openalex.org/W2130140866","https://openalex.org/W2135031801","https://openalex.org/W2139090854","https://openalex.org/W2139309322","https://openalex.org/W2142398675","https://openalex.org/W2146279773","https://openalex.org/W2155784960","https://openalex.org/W2156689656","https://openalex.org/W2156812875","https://openalex.org/W2164481421","https://openalex.org/W2164848770","https://openalex.org/W2169394328","https://openalex.org/W2171989929","https://openalex.org/W2187061649","https://openalex.org/W2543897149"],"related_works":["https://openalex.org/W2187061649","https://openalex.org/W2119646260","https://openalex.org/W2160415569","https://openalex.org/W128405245","https://openalex.org/W2120780777","https://openalex.org/W4293868931","https://openalex.org/W7095297258","https://openalex.org/W7096825073","https://openalex.org/W4400581401","https://openalex.org/W1613040537"],"abstract_inverted_index":{"Fast":[0],"Fourier":[1],"transform":[2],"(FFT)":[3],"has":[4,71,120],"become":[5],"ubiquitous":[6],"in":[7,19,75,100,192,244],"many":[8,20,197],"engineering":[9],"applications.":[10],"FFT":[11,39,58,70,89,107,171,207,215,220,227,234],"is":[12,145,185,256],"one":[13,186],"of":[14,35,45,49,59,77,81,103,112,128,169,187,196,214,267],"the":[15,33,42,64,68,82,101,126,166,174,188,265,272],"most":[16,189],"employed":[17],"blocks":[18],"communication":[21],"and":[22,52,87,94,150,161,172,179],"signal":[23],"processing":[24],"systems.":[25,199],"Efficient":[26],"algorithms":[27,40,96],"are":[28,53],"being":[29,257],"designed":[30,154],"to":[31,85,125,271],"improve":[32],"architecture":[34,83],"FFT.":[36],"Higher":[37],"radix":[38],"have":[41,97,209,242],"traditional":[43],"advantage":[44],"using":[46,177,216],"less":[47],"number":[48],"computational":[50],"elements":[51],"more":[54],"suitable":[55],"for":[56,155,205,259],"calculating":[57],"long":[60],"data":[61,151],"sequence.":[62],"Among":[63],"different":[65,104,206],"proposed":[66,105,240,268],"algorithms,":[67],"split-radix":[69,95],"shown":[72],"considerable":[73],"improvement":[74],"terms":[76],"reducing":[78],"hardware":[79],"complexity":[80],"compared":[84,270],"radix-2":[86],"radix-4":[88],"algorithms.":[90],"Here":[91],"radix-4,":[92],"radix-8,":[93],"been":[98,210],"used":[99,190,258],"design":[102,251],"complex":[106],"cores.":[108],"The":[109,140,163,239,262],"growing":[110],"popularity":[111],"adopting":[113],"virtual":[114],"instrumentation":[115],"(modular,":[116],"customizable,":[117],"software-defined":[118],"instrumentation)":[119],"only":[121],"became":[122],"possible":[123],"due":[124],"use":[127],"LabVIEW":[129,178],"with":[130],"a":[131],"highly":[132],"interactive":[133],"process":[134,254],"known":[135],"as":[136,247,249],"graphical":[137],"system":[138,153],"design.":[139],"CompactRIO":[141,217],"programmable":[142],"automation":[143],"controller":[144],"an":[146],"advanced":[147],"embedded":[148],"control":[149],"acquisition":[152],"applications":[156],"that":[157],"require":[158],"high":[159],"performance":[160],"reliability.":[162],"work":[164],"explains":[165],"real-time":[167],"implementation":[168,213],"256-point":[170],"finding":[173],"power":[175],"spectrum":[176],"CompactRIO.":[180],"New":[181],"distributed":[182],"arithmetic":[183],"(NEDA)":[184],"techniques":[191],"implementing":[193],"multiplier-less":[194],"architectures":[195,204],"digital":[198],"In":[200],"this":[201],"thesis,":[202],"four":[203],"cores":[208],"proposed:":[211],"\u2022\tReal-time":[212],"\u2022\t32-Point":[218],"Complex":[219,226,233],"Core":[221,228,235],"Using":[222,229,236],"Split-Radix":[223],"Algorithm":[224,231,238],"\u2022\t64-Point":[225,232],"Radix-4":[230],"Radix-8":[237],"designs":[241,269],"implemented":[243],"both":[245],"FPGA":[246],"well":[248],"ASIC":[250,260],"flows.":[252],"180nm":[253],"technology":[255],"implementation.":[261],"results":[263],"show":[264],"improvements":[266],"other":[273],"existing":[274],"architectures.":[275]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}