{"id":"https://openalex.org/W74949829","doi":null,"title":"VSIPL++/FPGA Design Methodology","display_name":"VSIPL++/FPGA Design Methodology","publication_year":2004,"publication_date":"2004-08-20","ids":{"openalex":"https://openalex.org/W74949829","mag":"74949829"},"language":"en","primary_location":{"id":"pmh:ADA428797","doi":null,"is_oa":false,"landing_page_url":"http://oai.dtic.mil/oai/oai?&amp;verb=getRecord&amp;metadataPrefix=html&amp;identifier=ADA428797","pdf_url":null,"source":{"id":"https://openalex.org/S4406923043","display_name":"Defense Technical Information Center (DTIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DTIC AND NTIS","raw_type":"Text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009112865","display_name":"Jules P. Bergmann","orcid":"https://orcid.org/0000-0002-5687-479X","observed_orcids":["https://orcid.org/0000-0002-5687-479X"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jules Bergmann","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047583039","display_name":"Susan Emeny","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Susan Emeny","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5051040926","display_name":"Peter Bronowicz","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peter Bronowicz","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9734,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.80588315,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-software-co-design","display_name":"hardware-software co-design","score":0.859000027179718},{"id":"https://openalex.org/keywords/fpga-design","display_name":"FPGA design","score":0.734000027179718},{"id":"https://openalex.org/keywords/stream-interface","display_name":"stream interfaces","score":0.5590000152587891},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.699999988079071},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"register transfer level","score":0.5809999704360962},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.6200000047683716},{"id":"https://openalex.org/keywords/macrocells","display_name":"macrocells","score":0.45100000500679016},{"id":"https://openalex.org/keywords/embedded-software","display_name":"embedded software","score":0.5600000023841858},{"id":"https://openalex.org/keywords/signal-and-image-processing","display_name":"signal and image processing","score":0.7039999961853027},{"id":"https://openalex.org/keywords/application-acceleration","display_name":"application acceleration","score":0.5320000052452087},{"id":"https://openalex.org/keywords/hardware-software-interface","display_name":"hardware-software interface","score":0.41600000858306885}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6950035691261292},{"id":"https://openalex.org/C161394538","wikidata":"https://www.wikidata.org/wiki/Q3127397","display_name":"Hardware compatibility list","level":4,"score":0.6884015202522278},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.645621657371521},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.593411386013031},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5327774286270142},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5290694832801819},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.5208445191383362},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5082396864891052},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4643694758415222},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4459995925426483},{"id":"https://openalex.org/C52913732","wikidata":"https://www.wikidata.org/wiki/Q857102","display_name":"Software design","level":4,"score":0.4385635256767273},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.41946518421173096},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.41738301515579224},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.35168910026550293},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20422762632369995}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:ADA428797","doi":null,"is_oa":false,"landing_page_url":"http://oai.dtic.mil/oai/oai?&amp;verb=getRecord&amp;metadataPrefix=html&amp;identifier=ADA428797","pdf_url":null,"source":{"id":"https://openalex.org/S4406923043","display_name":"Defense Technical Information Center (DTIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DTIC AND NTIS","raw_type":"Text"},{"id":"mag:74949829","doi":null,"is_oa":false,"landing_page_url":"http://www.ll.mit.edu/HPEC/agendas/proc03/abstracts/bergmann_rev1C.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.428600013256073,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W7100268152","https://openalex.org/W281515369","https://openalex.org/W2107526733","https://openalex.org/W2010398371","https://openalex.org/W4243255236","https://openalex.org/W2115959869","https://openalex.org/W2155392824","https://openalex.org/W269131234","https://openalex.org/W4246686620","https://openalex.org/W333060766"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,21,54,66,76,127,134,149,194,215],"hardware/software":[4,85],"codesign":[5],"methodology":[6,14,49,74,78,209],"for":[7,17,116,186,201,232],"hybrid":[8],"hardware":[9,24,31,60,70,100,123,177],"and":[10,20,35,44,61,63,71,89,92,101,141,157,174,203,221,229],"software":[11,18,62,102,207,235],"systems.":[12],"The":[13,30,48,73,143,191,237],"integrates":[15],"VSIPL++":[16],"design":[19,25,32,77,124,144,208],"portable,":[22],"composable":[23],"method":[26],"based":[27],"on":[28],"streams.":[29],"is":[33,245],"portable":[34],"scalable":[36],"from":[37,79],"design/test":[38],"systems":[39,83],"to":[40,45,81,103,217],"the":[41,97,110,218,252],"target":[42],"system":[43,90],"future":[46],"technologies.":[47],"increases":[50],"productivity":[51,230],"by":[52,64],"providing":[53,65],"concise":[55],"function":[56],"description":[57,132],"in":[58,133],"both":[59],"streamlined":[67],"interface":[68,196],"between":[69,189],"software.":[72],"supports":[75],"algorithms":[80],"embedded":[82,233],"with":[84,197],"co-design,":[86],"strong":[87],"unit":[88],"testing,":[91],"virtual":[93],"breadboarding.":[94],"It":[95,108],"simplifies":[96],"integration":[98],"of":[99,112,151,163],"create":[104],"high":[105,171],"performance":[106],"applications.":[107],"enables":[109],"use":[111,183],"predefined":[113],"FPGA":[114],"libraries":[115],"application":[117],"acceleration.":[118],"A":[119],"standard":[120],"high-level":[121],"synthesis":[122],"methodology,":[125],"using":[126,212],"register":[128],"Transfer":[129],"Logic":[130],"(RTL)":[131],"Hardware":[135,181],"Design":[136],"Language":[137],"(HDL),":[138],"achieves":[139],"portability":[140],"scalability.":[142],"can":[145],"be":[146],"synthesized":[147],"onto":[148],"range":[150],"Field":[152],"Programmable":[153],"Gate":[154],"Arrays":[155],"(FPGAs)":[156],"Application-Specific":[158],"Integrated":[159],"Circuits":[160],"(ASICs).":[161],"Encapsulation":[162],"device":[164],"specific":[165],"optimizations":[166],"into":[167],"macro":[168],"cells":[169],"ensures":[170],"performance.":[172],"Composable":[173],"highly":[175],"reusable":[176],"units":[178,182],"increase":[179],"productivity.":[180],"standardized":[184],"interfaces":[185],"data":[187],"exchange":[188],"them.":[190],"authors":[192],"chose":[193],"stream":[195],"flow":[198],"control,":[199],"appropriate":[200],"signal":[202],"image":[204],"processing.":[205],"Their":[206],"builds":[210],"applications":[211],"VSIPL++1.":[213],"VSIPL++,":[214],"successor":[216],"Vector":[219],"Signal":[220],"Image":[222],"Processing":[223],"Library":[224],"(VSIPL),":[225],"addresses":[226],"portability,":[227],"performance,":[228],"issues":[231],"high-performance":[234],"design.":[236],"High":[238],"Performance":[239],"Embedded":[240],"Computing":[241],"Software":[242],"Initiative":[243],"(HPEC-SI)2":[244],"standardizing":[246],"VSIPL++.":[247],"Thirty-five":[248],"briefing":[249],"charts":[250],"summarize":[251],"presentation.":[253]},"counts_by_year":[],"updated_date":"2026-09-22T06:50:58.402377","created_date":"2016-06-24T00:00:00"}
