{"id":"https://openalex.org/W7225744036","doi":"https://doi.org/10.14445/22315381/ijett-v74i10p137","title":"A Hybrid Analytical-Machine Learning Framework for Performance and Energy Modelling of CPU-FPGA Heterogeneous Architectures","display_name":"A Hybrid Analytical-Machine Learning Framework for Performance and Energy Modelling of CPU-FPGA Heterogeneous Architectures","publication_year":2026,"publication_date":"2026-11-10","ids":{"openalex":"https://openalex.org/W7225744036","doi":"https://doi.org/10.14445/22315381/ijett-v74i10p137"},"language":"en","primary_location":{"id":"doi:10.14445/22315381/ijett-v74i10p137","doi":"https://doi.org/10.14445/22315381/ijett-v74i10p137","is_oa":false,"landing_page_url":"https://doi.org/10.14445/22315381/ijett-v74i10p137","pdf_url":null,"source":{"id":"https://openalex.org/S4210182968","display_name":"International Journal of Engineering Trends and Technology","issn_l":"2231-5381","issn":["2231-5381","2349-0918"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["poland-20"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Engineering Trends and Technology","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5161386052","display_name":"Sabbar Hadi Salh","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sabbar Hadi Salh","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5145723422","display_name":"Maher Shahatha Mahmood","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Maher Shahatha Mahmood","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5139248424","display_name":"Methaq Kadhum Hussain","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Methaq Kadhum Hussain","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5139224744","display_name":"NoorAldeen R. Hamza","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nooraldeen R. Hamza","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"74","issue":"10","first_page":"530","last_page":"546"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.003800000064074993,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0013000000035390258,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.65420001745224},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.4894999861717224},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4867999851703644},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.47380000352859497},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.4666999876499176},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.43209999799728394},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.4316999912261963},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.4140999913215637},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.39309999346733093},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38510000705718994},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3718000054359436},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.36489999294281006},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.34940001368522644},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.34860000014305115},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.3197999894618988},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2930000126361847},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.29030001163482666},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.287200003862381},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2858999967575073},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.26919999718666077},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26409998536109924},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.26330000162124634},{"id":"https://openalex.org/C12725497","wikidata":"https://www.wikidata.org/wiki/Q810247","display_name":"Baseline (sea)","level":2,"score":0.26190000772476196},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.26010000705718994},{"id":"https://openalex.org/C170130773","wikidata":"https://www.wikidata.org/wiki/Q216378","display_name":"Usability","level":2,"score":0.2547999918460846},{"id":"https://openalex.org/C2777115002","wikidata":"https://www.wikidata.org/wiki/Q7168246","display_name":"Performance prediction","level":2,"score":0.2529999911785126}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.14445/22315381/ijett-v74i10p137","doi":"https://doi.org/10.14445/22315381/ijett-v74i10p137","is_oa":false,"landing_page_url":"https://doi.org/10.14445/22315381/ijett-v74i10p137","pdf_url":null,"source":{"id":"https://openalex.org/S4210182968","display_name":"International Journal of Engineering Trends and Technology","issn_l":"2231-5381","issn":["2231-5381","2349-0918"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["poland-20"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Engineering Trends and Technology","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Modern":[0],"data":[1],"centres":[2],"increasingly":[3],"employ":[4],"heterogeneous":[5,84],"computing":[6],"platforms":[7,27],"that":[8,251],"combine":[9],"Field-Programmable":[10],"Gate":[11],"Arrays":[12],"(FPGAs)":[13],"with":[14,186,225],"general-purpose":[15],"processors":[16],"to":[17,99,238],"improve":[18],"performance":[19,78,254],"and":[20,39,57,79,94,104,115,122,159,181,201,255,283],"energy":[21,80,109,232,256],"efficiency.":[22],"The":[23,86,170],"effectiveness":[24],"of":[25,33,82,118,197,210,218,276],"these":[26],"depends":[28],"strongly":[29],"on":[30,129],"the":[31,36,40,113,120,133,164,221,241,252,261,266],"level":[32],"coupling":[34,175,278],"between":[35,53],"host":[37],"CPU":[38,121],"reconfigurable":[41],"fabric.":[42],"Existing":[43],"approaches":[44],"for":[45,65,77,112,141,199,203,227,273],"evaluating":[46],"CPU-FPGA":[47,83,277],"systems":[48],"often":[49],"involve":[50],"a":[51,73,89,95,207,216,269],"trade-off":[52],"simplified":[54],"analytical":[55,134],"models":[56],"computationally":[58,137,270],"expensive":[59],"detailed":[60],"simulations,":[61],"limiting":[62],"their":[63],"suitability":[64],"large-scale":[66,142],"early":[67,274],"design-space":[68,143],"exploration.":[69,144],"This":[70],"paper":[71],"presents":[72],"hybrid":[74],"analytical-machine-learning":[75],"framework":[76,87,171,267],"modelling":[81],"architectures.":[85],"introduces":[88],"workload-adaptive":[90],"overlap":[91,103],"function":[92],"\u03b3(N)":[93],"bus-contention":[96],"factor":[97],"\u03ba":[98],"represent":[100],"workload-dependent":[101],"communication-computation":[102],"communication":[105],"contention.":[106],"A":[107,124,245],"dual-state":[108],"model":[110],"accounts":[111],"active":[114],"idle":[116],"power":[117],"both":[119],"FPGA.":[123],"Gradient-Boosted-Tree":[125],"(GBT)":[126],"surrogate,":[127],"trained":[128],"samples":[130],"generated":[131],"by":[132,154,234],"model,":[135],"provides":[136,268],"efficient":[138,271],"repeated":[139],"evaluations":[140],"An":[145],"Adaptive":[146],"Coupling":[147],"Selector":[148],"(ACS)":[149],"further":[150,249],"supports":[151],"architecture":[152],"selection":[153],"considering":[155],"Energy-Delay":[156],"Product":[157],"(EDP)":[158],"normalized":[160],"deployment":[161],"cost":[162],"in":[163],"(N,w":[165],"E":[166],")":[167],"decision":[168],"space.":[169],"evaluates":[172],"three":[173],"representative":[174,208],"topologies:":[176],"External":[177],"(EXT),":[178],"Shared-Memory":[179],"(SHM),":[180],"on-die":[182],"Coprocessor":[183],"(COP).":[184],"Comparison":[185],"five":[187],"published":[188],"FPGA":[189],"benchmarks":[190],"yields":[191],"Mean":[192],"Absolute":[193],"Percentage":[194],"Errors":[195],"(MAPE)":[196],"4.4%":[198],"speed-up":[200,217],"7.0%":[202],"total":[204,231],"energy.":[205],"At":[206],"workload":[209],"N=10":[211],"8":[212],"operations,":[213],"COP":[214],"achieves":[215],"1.20\u00d7":[219],"over":[220],"CPU-only":[222],"baseline,":[223],"compared":[224],"0.39\u00d7":[226],"EXT,":[228],"while":[229],"reducing":[230],"consumption":[233],"approximately":[235],"57.7%":[236],"relative":[237,253],"EXT":[239],"under":[240,260,280],"evaluated":[242],"baseline":[243],"parameters.":[244],"5,000-trial":[246],"Monte-Carlo":[247],"analysis":[248],"indicates":[250],"trends":[257],"remain":[258],"stable":[259],"considered":[262],"parameter":[263],"perturbations.":[264],"Overall,":[265],"approach":[272],"exploration":[275],"alternatives":[279],"performance,":[281],"energy,":[282],"deployment-cost":[284],"considerations.":[285]},"counts_by_year":[],"updated_date":"2026-11-11T12:16:26.678958","created_date":"2026-11-11T00:00:00"}
