{"id":"https://openalex.org/W7225734827","doi":"https://doi.org/10.1007/s44291-026-00311-x","title":"Design and implementation of a high-speed reversible arithmetic logic unit for power-efficient computing","display_name":"Design and implementation of a high-speed reversible arithmetic logic unit for power-efficient computing","publication_year":2026,"publication_date":"2026-11-10","ids":{"openalex":"https://openalex.org/W7225734827","doi":"https://doi.org/10.1007/s44291-026-00311-x"},"language":"en","primary_location":{"id":"doi:10.1007/s44291-026-00311-x","doi":"https://doi.org/10.1007/s44291-026-00311-x","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s44291-026-00311-x","pdf_url":null,"source":{"id":"https://openalex.org/S5407036633","display_name":"Discover Electronics","issn_l":"2948-1600","issn":["2948-1600"],"is_oa":true,"is_in_doaj":true,"is_core":false,"listed_in":["doaj"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Discover Electronics","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://doi.org/10.1007/s44291-026-00311-x","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108861104","display_name":"Mihir Lal Saha","orcid":"https://orcid.org/0009-0005-9090-7697","observed_orcids":["https://orcid.org/0009-0005-9090-7697"]},"institutions":[{"id":"https://openalex.org/I1296725772","display_name":"University of Engineering & Management","ror":"https://ror.org/02decng19","country_code":"IN","type":"education","lineage":["https://openalex.org/I1296725772"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mihir Lal Saha","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Institute of Engineering and Management, Kolkata, School of University of Engineering and Management, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Institute of Engineering and Management, Kolkata, School of University of Engineering and Management, Kolkata, India","institution_ids":["https://openalex.org/I1296725772"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069639441","display_name":"Agnik Maity","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1296725772","display_name":"University of Engineering & Management","ror":"https://ror.org/02decng19","country_code":"IN","type":"education","lineage":["https://openalex.org/I1296725772"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Agnik Maity","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Institute of Engineering and Management, Kolkata, School of University of Engineering and Management, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Institute of Engineering and Management, Kolkata, School of University of Engineering and Management, Kolkata, India","institution_ids":["https://openalex.org/I1296725772"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5141170689","display_name":"Antarik Sinha","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1296725772","display_name":"University of Engineering & Management","ror":"https://ror.org/02decng19","country_code":"IN","type":"education","lineage":["https://openalex.org/I1296725772"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Antarik Sinha","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Institute of Engineering and Management, Kolkata, School of University of Engineering and Management, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Institute of Engineering and Management, Kolkata, School of University of Engineering and Management, Kolkata, India","institution_ids":["https://openalex.org/I1296725772"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5108861104"],"corresponding_institution_ids":["https://openalex.org/I1296725772"],"apc_list":{"value":0,"currency":"USD","value_usd":0},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9765999913215637,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9765999913215637,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0210999995470047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8136000037193298},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.6995000243186951},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6887999773025513},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5837000012397766},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5637999773025513},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5249000191688538},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5217999815940857},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47189998626708984},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4521999955177307},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4406000077724457},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.43810001015663147},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41110000014305115},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3840999901294708},{"id":"https://openalex.org/C81988521","wikidata":"https://www.wikidata.org/wiki/Q676838","display_name":"Control unit","level":2,"score":0.3837999999523163},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.37689998745918274},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36489999294281006},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.3334999978542328},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.3255999982357025},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.325300008058548},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.3240000009536743},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.321399986743927},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.304500013589859},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.29339998960494995},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.2921999990940094},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.27889999747276306},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.2648000121116638},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26030001044273376},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.2524000108242035}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s44291-026-00311-x","doi":"https://doi.org/10.1007/s44291-026-00311-x","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s44291-026-00311-x","pdf_url":null,"source":{"id":"https://openalex.org/S5407036633","display_name":"Discover Electronics","issn_l":"2948-1600","issn":["2948-1600"],"is_oa":true,"is_in_doaj":true,"is_core":false,"listed_in":["doaj"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Discover Electronics","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1007/s44291-026-00311-x","doi":"https://doi.org/10.1007/s44291-026-00311-x","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s44291-026-00311-x","pdf_url":null,"source":{"id":"https://openalex.org/S5407036633","display_name":"Discover Electronics","issn_l":"2948-1600","issn":["2948-1600"],"is_oa":true,"is_in_doaj":true,"is_core":false,"listed_in":["doaj"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Discover Electronics","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2035112473","https://openalex.org/W2105259569","https://openalex.org/W2159848982","https://openalex.org/W2573930928","https://openalex.org/W2748619718","https://openalex.org/W2772383648","https://openalex.org/W2931524400","https://openalex.org/W2947126641","https://openalex.org/W3020987849","https://openalex.org/W3104913350","https://openalex.org/W3191942676","https://openalex.org/W4211021386","https://openalex.org/W4233798822","https://openalex.org/W4313255222","https://openalex.org/W4364860039","https://openalex.org/W4391664482","https://openalex.org/W4392660397","https://openalex.org/W4393261297","https://openalex.org/W4406267728","https://openalex.org/W4409352070","https://openalex.org/W4416922471"],"related_works":[],"abstract_inverted_index":{"Abstract":[0],"This":[1],"paper":[2],"presents":[3],"the":[4,84,95,110,115],"design,":[5],"simulation,":[6],"and":[7,32,43,76,99,107],"hardware":[8],"validation":[9],"of":[10,27,57,126,134],"a":[11,50,60,123,130],"high-speed,":[12],"power-efficient":[13],"reversible":[14,36],"Arithmetic":[15],"Logic":[16,53],"Unit":[17],"(ALU)":[18],"architecture,":[19],"implemented":[20,100],"in":[21,73],"Verilog":[22],"HDL.":[23],"The":[24,46,119],"ALU":[25],"consists":[26],"three":[28],"modular":[29],"blocks\u2014Arithmetic,":[30],"Logical,":[31],"Control":[33],"Units\u2014and":[34],"employs":[35],"logic":[37],"gates":[38],"to":[39],"minimize":[40],"power":[41,133],"consumption":[42],"information":[44],"loss.":[45],"proposed":[47],"design":[48,96],"achieves":[49],"Total":[51],"Reversible":[52],"Instruction":[54],"Count":[55],"(TRLIC)":[56],"53,":[58],"reflecting":[59],"62.67%":[61],"improvement":[62],"over":[63],"prior":[64],"works.":[65],"Functional":[66],"verification":[67],"was":[68,97],"carried":[69],"out":[70],"through":[71],"simulation":[72],"Xilinx":[74],"Vivado":[75],"ISE":[77],"14.7,":[78],"followed":[79],"by":[80],"FPGA":[81,93],"prototyping":[82],"on":[83],"NEXYS":[85],"A7":[86],"(Artix-7)":[87],"board,":[88],"confirming":[89],"accurate":[90],"operation.":[91],"Beyond":[92],"validation,":[94],"synthesized":[98],"as":[101],"an":[102],"ASIC":[103,120],"using":[104],"Cadence":[105],"Genus":[106],"Innovus":[108],"with":[109,129],"90-nm":[111],"CMOS":[112],"technology,":[113],"completing":[114],"RTL-to-GDSII":[116],"physical-design":[117],"flow.":[118],"implementation":[121],"achieved":[122],"critical-path":[124],"delay":[125],"1.195":[127],"ns,":[128],"reported":[131],"switching":[132],"1.72":[135],"\u00b5W.":[136]},"counts_by_year":[],"updated_date":"2026-11-11T12:16:26.678958","created_date":"2026-11-11T00:00:00"}
