{"id":"https://openalex.org/W7225148144","doi":"https://doi.org/10.1145/3861159","title":"SBLLocking: Localization of Optical Side-Channel Leakage in Logic-Locked Integrated Circuits through Structure-based Learning","display_name":"SBLLocking: Localization of Optical Side-Channel Leakage in Logic-Locked Integrated Circuits through Structure-based Learning","publication_year":2026,"publication_date":"2026-11-03","ids":{"openalex":"https://openalex.org/W7225148144","doi":"https://doi.org/10.1145/3861159"},"language":"en","primary_location":{"id":"doi:10.1145/3861159","doi":"https://doi.org/10.1145/3861159","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3861159","pdf_url":null,"source":{"id":"https://openalex.org/S96198239","display_name":"ACM Journal on Emerging Technologies in Computing Systems","issn_l":"1550-4832","issn":["1550-4832","1550-4840"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-c","cwts-core","dongbi-b","jufo-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Journal on Emerging Technologies in Computing Systems","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020490663","display_name":"Yuyang Wang","orcid":"https://orcid.org/0009-0005-4492-1594","observed_orcids":["https://orcid.org/0009-0005-4492-1594","https://orcid.org/0000-0002-0139-879X"]},"institutions":[{"id":"https://openalex.org/I121934306","display_name":"Tufts University","ror":"https://ror.org/05wvpxv85","country_code":"US","type":"education","lineage":["https://openalex.org/I121934306"]},{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuyang Wang","raw_affiliation_strings":["Rochester Institute of Technology, USA and Tufts University, USA"],"raw_orcid":"https://orcid.org/0009-0005-4492-1594","affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology, USA and Tufts University, USA","institution_ids":["https://openalex.org/I121934306","https://openalex.org/I155173764"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026885733","display_name":"Robi Paul","orcid":"https://orcid.org/0000-0002-7367-8432","observed_orcids":["https://orcid.org/0000-0002-7367-8432"]},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robi Paul","raw_affiliation_strings":["Rochester Institute of Technology, USA"],"raw_orcid":"https://orcid.org/0000-0002-7367-8432","affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology, USA","institution_ids":["https://openalex.org/I155173764"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077915520","display_name":"Michael Zuzak","orcid":"https://orcid.org/0000-0003-0356-9393","observed_orcids":["https://orcid.org/0000-0003-0356-9393"]},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Zuzak","raw_affiliation_strings":["Rochester Institute of Technology, USA"],"raw_orcid":"https://orcid.org/0000-0003-0356-9393","affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology, USA","institution_ids":["https://openalex.org/I155173764"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.87774015,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13999","display_name":"Digital Rights Management and Security","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-locking","display_name":"logic locking","score":0.9940000176429749},{"id":"https://openalex.org/keywords/side-channel-leakage","display_name":"side-channel leakage","score":0.7720000147819519},{"id":"https://openalex.org/keywords/clap","display_name":"CLAP","score":0.7710000276565552},{"id":"https://openalex.org/keywords/hardware-obfuscation","display_name":"hardware obfuscation","score":0.6679999828338623}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9226999878883362},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6872000098228455},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6175000071525574},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5253999829292297},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.512499988079071},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.477400004863739},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.475600004196167},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.46380001306533813},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.44429999589920044},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4189000129699707},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3783000111579895},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3772999942302704},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.3686999976634979},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.33809998631477356},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.31630000472068787},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.3050999939441681},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.30070000886917114},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.28700000047683716},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2867000102996826},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.28630000352859497},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2766000032424927},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.2743000090122223},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.27410000562667847},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.2590999901294708},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.2578999996185303},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.2565000057220459},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2565000057220459},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2540000081062317}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3861159","doi":"https://doi.org/10.1145/3861159","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3861159","pdf_url":null,"source":{"id":"https://openalex.org/S96198239","display_name":"ACM Journal on Emerging Technologies in Computing Systems","issn_l":"1550-4832","issn":["1550-4832","1550-4840"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-c","cwts-core","dongbi-b","jufo-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Journal on Emerging Technologies in Computing Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2010633842","https://openalex.org/W2095410905","https://openalex.org/W2153843906","https://openalex.org/W2343475170","https://openalex.org/W2945305016","https://openalex.org/W2977663466","https://openalex.org/W2985331920","https://openalex.org/W3111561387","https://openalex.org/W3125917269","https://openalex.org/W3177097405","https://openalex.org/W4213073217","https://openalex.org/W4312389853","https://openalex.org/W4318580662","https://openalex.org/W4402192457","https://openalex.org/W4406936933","https://openalex.org/W4415366545"],"related_works":["https://openalex.org/W3182286741","https://openalex.org/W4379115967","https://openalex.org/W4406936933","https://openalex.org/W4395110351","https://openalex.org/W2942805026","https://openalex.org/W4312307961","https://openalex.org/W7165158741","https://openalex.org/W4384471459","https://openalex.org/W2766393343","https://openalex.org/W4414404784"],"abstract_inverted_index":{"Logic":[0],"locking":[1,25],"protects":[2],"outsourced":[3],"integrated":[4],"circuit":[5,9,52,166],"designs":[6],"by":[7],"obfuscating":[8],"functionality,":[10],"thereby":[11],"hindering":[12],"reverse":[13],"engineering,":[14],"piracy,":[15],"and":[16,70,81,84,93,124,134,150,169],"overproduction.":[17],"However,":[18],"prior":[19],"work":[20],"has":[21],"shown":[22],"that":[23,48],"logic":[24,91],"is":[26,105],"vulnerable":[27,51],"to":[28,96],"physical":[29],"probing":[30],"attacks":[31],"such":[32],"as":[33,77],"Electro-optical":[34],"Frequency":[35],"Mapping":[36],"(EOFM).":[37],"In":[38,101],"this":[39,102],"work,":[40],"we":[41],"present":[42],"SBLLocking,":[43],"a":[44,57,74,78,135,171],"structure-based":[45],"learning":[46],"framework":[47],"identifies":[49],"potentially":[50],"regions":[53],"before":[54],"fabrication.":[55],"As":[56],"pre-silicon":[58],"screening":[59],"tool,":[60],"SBLLocking":[61,119,128,159],"helps":[62],"designers":[63],"identify":[64,97],"candidate":[65,98],"nodes":[66],"for":[67,167,184],"further":[68],"validation":[69],"mitigation.":[71],"It":[72],"represents":[73],"gate-level":[75],"netlist":[76],"directed":[79],"graph":[80],"uses":[82],"structural":[83],"logic-derived":[85],"features,":[86],"including":[87],"gate":[88],"type,":[89],"connectivity,":[90],"level,":[92],"key-input":[94],"dependence,":[95],"EOFM-susceptible":[99],"nodes.":[100],"study,":[103],"susceptibility":[104,188],"operationally":[106],"defined":[107],"using":[108],"the":[109],"SAT-based":[110],"key-dependent":[111],"distinguishability":[112],"criterion":[113],"introduced":[114],"in":[115,139],"CLAP.":[116],"We":[117],"evaluated":[118],"on":[120,147,154],"500":[121],"unseen":[122],"benchmark-derived":[123,148],"synthetically":[125],"generated":[126],"circuits.":[127],"achieved":[129,170],"95.71%":[130],"average":[131],"node-level":[132,178],"accuracy":[133],"1.72%":[136],"false-negative":[137],"rate":[138],"identifying":[140],"CLAP-susceptible":[141],"leaking":[142],"nodes,":[143],"with":[144],"stronger":[145],"performance":[146],"circuits":[149],"only":[151],"minor":[152],"degradation":[153],"structurally":[155],"diverse":[156],"synthetic":[157],"designs.":[158],"required":[160],"approximately":[161],"\\(2\\times":[162],"10^{-3}\\)":[163],"s":[164],"per":[165],"inference":[168],"\\(1.63\\times":[172],"10^{8}\\)":[173],"runtime":[174],"speedup":[175],"over":[176],"exhaustive":[177],"SAT":[179],"analysis,":[180],"demonstrating":[181],"its":[182],"practicality":[183],"scalable":[185],"design-time":[186],"EOFM":[187],"screening.":[189]},"counts_by_year":[],"updated_date":"2026-11-05T12:25:35.769452","created_date":"2026-11-04T00:00:00"}