{"id":"https://openalex.org/W7224947211","doi":"https://doi.org/10.1109/icosics70095.2026.11746585","title":"BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM2-DSA Accelerator","display_name":"BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM2-DSA Accelerator","publication_year":2026,"publication_date":"2026-09-01","ids":{"openalex":"https://openalex.org/W7224947211","doi":"https://doi.org/10.1109/icosics70095.2026.11746585"},"language":"en","primary_location":{"id":"doi:10.1109/icosics70095.2026.11746585","doi":"https://doi.org/10.1109/icosics70095.2026.11746585","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icosics70095.2026.11746585","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Secure IoT and Cybersecurity (ICOSICS)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/icosics70095.2026.11746585","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5157771981","display_name":"Mahima Agarwal","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mahima Agarwal","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025400168","display_name":"Harish Kumar G R","orcid":"https://orcid.org/0000-0003-2302-5828","observed_orcids":["https://orcid.org/0000-0003-2302-5828"]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Harish Kumar G","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5160210719","display_name":"Dilna H K","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dilna H K","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107897811","display_name":"Raja Sekar Kumaresan","orcid":"https://orcid.org/0000-0002-7541-4203","observed_orcids":["https://orcid.org/0000-0002-7541-4203"]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Raja Sekar K","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022564712","display_name":"Aneesh Raveendran","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aneesh Raveendran","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028262376","display_name":"Vivian Desalphine","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vivian Desalphine","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1331500379"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1000","last_page":"1005"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.5723000168800354,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.5723000168800354,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.20260000228881836,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.08810000121593475,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/trusted-platform-module","display_name":"Trusted Platform Module","score":0.8230000138282776},{"id":"https://openalex.org/keywords/cryptographic-hardware-accelerators","display_name":"cryptographic hardware accelerator","score":0.8519999980926514},{"id":"https://openalex.org/keywords/key-generation","display_name":"key generation","score":0.656000018119812},{"id":"https://openalex.org/keywords/scalar-multiplication","display_name":"scalar multiplication","score":0.8080000281333923},{"id":"https://openalex.org/keywords/modular-arithmetic","display_name":"modular arithmetic","score":0.972000002861023},{"id":"https://openalex.org/keywords/risc-v-soc","display_name":"RISC-V SoC","score":0.6399999856948853},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.4399999976158142},{"id":"https://openalex.org/keywords/asic-synthesis","display_name":"ASIC synthesis","score":0.6899999976158142}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5674999952316284},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.541700005531311},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4117000102996826},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3714999854564667},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32190001010894775},{"id":"https://openalex.org/C147494362","wikidata":"https://www.wikidata.org/wiki/Q2078905","display_name":"Troubleshooting","level":2,"score":0.32010000944137573},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26589998602867126},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25760000944137573},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.2538999915122986},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.24879999458789825}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icosics70095.2026.11746585","doi":"https://doi.org/10.1109/icosics70095.2026.11746585","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icosics70095.2026.11746585","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Secure IoT and Cybersecurity (ICOSICS)","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1109/icosics70095.2026.11746585","doi":"https://doi.org/10.1109/icosics70095.2026.11746585","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icosics70095.2026.11746585","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Secure IoT and Cybersecurity (ICOSICS)","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.651199996471405}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W2104148409","https://openalex.org/W2120667087","https://openalex.org/W2760385239","https://openalex.org/W2799159489","https://openalex.org/W2913330080","https://openalex.org/W2927650403","https://openalex.org/W2936783673","https://openalex.org/W2938677346","https://openalex.org/W2955998213","https://openalex.org/W2971644775","https://openalex.org/W2996409367","https://openalex.org/W3005961764","https://openalex.org/W3108978602","https://openalex.org/W4200585519","https://openalex.org/W4229440577","https://openalex.org/W4283723350","https://openalex.org/W4312575571","https://openalex.org/W4312684437","https://openalex.org/W4315778323","https://openalex.org/W4363647425","https://openalex.org/W4389459305","https://openalex.org/W4409097684","https://openalex.org/W4412405545","https://openalex.org/W7137896524"],"related_works":["https://openalex.org/W7224869080","https://openalex.org/W7220678568","https://openalex.org/W2558432655","https://openalex.org/W100391727","https://openalex.org/W3207840427","https://openalex.org/W7165879764","https://openalex.org/W7017440177","https://openalex.org/W3005322069","https://openalex.org/W4242078595","https://openalex.org/W7055092158"],"abstract_inverted_index":{"Trusted":[0],"Platform":[1],"Modules":[2],"(TPMs)":[3],"serve":[4],"as":[5,22,38,93,199],"hardware":[6,53,83,201],"roots":[7],"of":[8,62],"trust":[9],"in":[10,73,154,191],"secure":[11,23],"System":[12],"on":[13,170,186],"Chip":[14],"(SoC)":[15],"environments,":[16],"supporting":[17],"essential":[18],"security":[19],"services":[20],"such":[21,37],"key":[24,31,34,134],"exchange,":[25],"digital":[26],"signatures,":[27],"authentication,":[28],"and":[29,55,111,124,138,146,157],"cryptographic":[30,35,65,89,161,213],"management.":[32],"Public":[33],"algorithms":[36],"the":[39,121,125,165,171,205],"SM2":[40,128],"Digital":[41],"Signature":[42],"Algorithm":[43],"(SM2":[44],"DSA)":[45],"are":[46],"fundamental":[47],"to":[48,99,115],"these":[49],"operations,":[50],"requiring":[51],"efficient":[52,143],"implementations":[54],"communication":[56],"interfaces.":[57],"However,":[58],"standalone":[59],"preintegration":[60],"validation":[61,84,101],"AXI":[63,87,100,126,211],"based":[64,88,97,113,207,212],"accelerators":[66],"through":[67],"a":[68,80,94,200],"serial":[69],"interface":[70,123],"remains":[71],"unaddressed":[72],"existing":[74],"literature.":[75],"This":[76],"research":[77],"paper":[78],"presents":[79],"deterministic,":[81],"reusable":[82],"framework":[85,105],"for":[86,209],"IP":[90],"cores,":[91],"realized":[92],"structured,":[95],"packet":[96],"SPI":[98,122],"architecture.":[102],"The":[103,131,150,195],"proposed":[104],"employs":[106],"dual":[107],"clock":[108],"domain":[109],"synchronization":[110],"FIFO":[112],"buffering":[114],"ensure":[116],"reliable":[117],"data":[118],"transfer":[119],"between":[120],"enabled":[127],"DSA":[129],"accelerator.":[130],"architecture":[132],"supports":[133],"generation,":[135,137],"signature":[136,139],"verification":[140,202],"operations":[141],"using":[142,159],"scalar":[144],"multiplication":[145],"modular":[147],"arithmetic":[148],"techniques.":[149],"design":[151,196],"is":[152],"implemented":[153],"Verilog":[155],"HDL":[156],"verified":[158],"standard":[160,193],"test":[162],"vectors":[163],"from":[164],"GM/T":[166],"0003":[167],"specification,":[168],"validated":[169],"Xilinx":[172],"Virtex":[173],"UltraScale":[174],"VCU118":[175],"FPGA":[176],"achieving":[177],"125":[178],"MHz":[179],"with":[180,183],"48880":[181],"LUTs":[182],"ASIC":[184],"synthesis":[185],"SCL":[187],"180":[188],"nm":[189],"resulting":[190],"2,62,253":[192],"cells.":[194],"further":[197],"serves":[198],"platform":[203],"within":[204],"RISC-V":[206],"BHARAT-TPM":[208],"validating":[210],"accelerator":[214],"cores.":[215]},"counts_by_year":[],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2026-10-31T00:00:00"}