{"id":"https://openalex.org/W7224869080","doi":"https://doi.org/10.1109/icosics70095.2026.11746777","title":"BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM4 Accelerator","display_name":"BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM4 Accelerator","publication_year":2026,"publication_date":"2026-09-01","ids":{"openalex":"https://openalex.org/W7224869080","doi":"https://doi.org/10.1109/icosics70095.2026.11746777"},"language":"en","primary_location":{"id":"doi:10.1109/icosics70095.2026.11746777","doi":"https://doi.org/10.1109/icosics70095.2026.11746777","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icosics70095.2026.11746777","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Secure IoT and Cybersecurity (ICOSICS)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/icosics70095.2026.11746777","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5160151932","display_name":"Jeeshma T. N","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jeeshma T. N","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5160191387","display_name":"Beautlin S","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Beautlin S","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5160204734","display_name":"Veena V","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Veena V","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107897811","display_name":"Raja Sekar Kumaresan","orcid":"https://orcid.org/0000-0002-7541-4203","observed_orcids":["https://orcid.org/0000-0002-7541-4203"]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Raja Sekar K","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022564712","display_name":"Aneesh Raveendran","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aneesh Raveendran","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028262376","display_name":"Vivian Desalphine","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vivian Desalphine","raw_affiliation_strings":["Centre for Development of Advanced Computing (C-DAC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing (C-DAC)","institution_ids":["https://openalex.org/I1331500379"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1331500379"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.78206121,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"132","last_page":"137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9702000021934509,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9702000021934509,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.013899999670684338,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.008899999782443047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sm4-block-cipher","display_name":"SM4 block cipher","score":0.6489999890327454},{"id":"https://openalex.org/keywords/cryptographic-accelerators","display_name":"cryptographic accelerators","score":0.7450000047683716},{"id":"https://openalex.org/keywords/trusted-platform-module","display_name":"Trusted Platform Module","score":0.7860000133514404},{"id":"https://openalex.org/keywords/spi-interface","display_name":"SPI interface","score":0.6990000009536743},{"id":"https://openalex.org/keywords/hardware-root-of-trust","display_name":"hardware root of trust","score":0.6269999742507935},{"id":"https://openalex.org/keywords/risc-v","display_name":"RISC-V","score":0.5630000233650208},{"id":"https://openalex.org/keywords/asic-synthesis","display_name":"ASIC synthesis","score":0.4449999928474426},{"id":"https://openalex.org/keywords/fpga-prototyping","display_name":"FPGA prototyping","score":0.6079999804496765}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6406000256538391},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5497999787330627},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5388000011444092},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3772999942302704},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34220001101493835},{"id":"https://openalex.org/C147494362","wikidata":"https://www.wikidata.org/wiki/Q2078905","display_name":"Troubleshooting","level":2,"score":0.27059999108314514},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2703999876976013},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.2639000117778778},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.2549999952316284}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icosics70095.2026.11746777","doi":"https://doi.org/10.1109/icosics70095.2026.11746777","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icosics70095.2026.11746777","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Secure IoT and Cybersecurity (ICOSICS)","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1109/icosics70095.2026.11746777","doi":"https://doi.org/10.1109/icosics70095.2026.11746777","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icosics70095.2026.11746777","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Secure IoT and Cybersecurity (ICOSICS)","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.7207000255584717,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W143815100","https://openalex.org/W2104148409","https://openalex.org/W2120667087","https://openalex.org/W2153130885","https://openalex.org/W2340164128","https://openalex.org/W2900600414","https://openalex.org/W2949699925","https://openalex.org/W2955998213","https://openalex.org/W3108978602","https://openalex.org/W3125000971","https://openalex.org/W3125662899","https://openalex.org/W4312575571","https://openalex.org/W4318185169","https://openalex.org/W4320075936","https://openalex.org/W4363647425","https://openalex.org/W4405938304","https://openalex.org/W4406164174","https://openalex.org/W4409097684","https://openalex.org/W4409724463","https://openalex.org/W4414940484","https://openalex.org/W7134215449","https://openalex.org/W7137896524"],"related_works":["https://openalex.org/W7224947211","https://openalex.org/W7220678568","https://openalex.org/W2558432655","https://openalex.org/W7165879764","https://openalex.org/W4409090236","https://openalex.org/W6982101914","https://openalex.org/W4312924909","https://openalex.org/W100391727","https://openalex.org/W7017440177","https://openalex.org/W4364356393"],"abstract_inverted_index":{"Trusted":[0],"Platform":[1],"Modules":[2],"(TPMs)":[3],"serve":[4],"as":[5,22,37,188],"hardware":[6,190],"roots":[7],"of":[8,48,76,157,175,181],"trust":[9],"in":[10,59,127],"secure":[11],"System":[12],"on":[13,132,163],"Chip":[14],"(SoC)":[15],"environments,":[16],"supporting":[17],"essential":[18],"security":[19],"services":[20],"such":[21,36],"message":[23],"confidentiality,":[24],"digital":[25],"signatures,":[26],"authentication,":[27],"and":[28,89,102,113,120,130,160,171],"cryptographic":[29,51,79,202],"key":[30],"management.":[31],"Symmetric":[32],"block":[33],"cipher":[34],"algorithms":[35],"SM4":[38,106,111,149],"are":[39],"fundamental":[40],"to":[41,93],"these":[42],"operations,":[43],"yet":[44],"standalone":[45,69],"preintegration":[46],"validation":[47,70,191],"AXI":[49,77,104,200],"based":[50,91,196,201],"accelerators":[52],"through":[53],"a":[54,66,140,155,172,189],"serial":[55],"interface":[56,101],"remains":[57],"unaddressed":[58],"existing":[60],"literature.":[61],"This":[62],"research":[63],"paper":[64],"presents":[65],"reusable":[67],"SPI-to-AXI":[68],"framework":[71,83],"for":[72,147,198],"independent":[73],"pre-integration":[74],"verification":[75],"enabled":[78,105],"accelerators.":[80],"The":[81,108,184],"proposed":[82],"employs":[84],"dual":[85],"clock":[86],"domain":[87],"synchronization":[88],"FIFO":[90],"buffering":[92],"ensure":[94],"reliable":[95],"data":[96],"transfer":[97],"between":[98],"the":[99,103,133,148,182,194],"SPI":[100],"accelerator.":[107],"design":[109,185],"supports":[110],"encryption":[112],"decryption":[114],"across":[115,151],"ECB,":[116],"CBC,":[117],"CFB,":[118],"OFB,":[119],"CTR":[121],"modes":[122],"per":[123],"GB/T":[124],"32907-2016,":[125],"implemented":[126],"Verilog":[128],"HDL":[129],"validated":[131],"Xilinx":[134],"Virtex":[135],"UltraScale+":[136],"VCU118":[137],"FPGA,":[138],"achieving":[139],"300.00":[141],"MHz":[142],"frequency":[143],"with":[144,154,167],"3678":[145],"LUTs":[146],"AXI-IP":[150],"all":[152],"modes,":[153],"throughput":[156],"1.2":[158],"Gbps,":[159],"ASIC":[161],"synthesis":[162],"SCL":[164],"180":[165],"nm":[166],"20,790":[168],"standard":[169],"cells":[170],"cell":[173],"area":[174],"0.622":[176],"mm2,":[177],"confirming":[178],"silicon":[179],"readiness":[180],"design.":[183],"further":[186],"serves":[187],"platform":[192],"within":[193],"RISC-V":[195],"BHARAT-TPM":[197],"validating":[199],"accelerator":[203],"cores.":[204]},"counts_by_year":[],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2026-10-31T00:00:00"}