{"id":"https://openalex.org/W7224796723","doi":"https://doi.org/10.20944/preprints202610.3021.v1","title":"An RV32IMC Processor with a Tightly Coupled Linear Classifier Accelerator for Edge AI Inference","display_name":"An RV32IMC Processor with a Tightly Coupled Linear Classifier Accelerator for Edge AI Inference","publication_year":2026,"publication_date":"2026-10-29","ids":{"openalex":"https://openalex.org/W7224796723","doi":"https://doi.org/10.20944/preprints202610.3021.v1"},"language":"en","primary_location":{"id":"doi:10.20944/preprints202610.3021.v1","doi":"https://doi.org/10.20944/preprints202610.3021.v1","is_oa":true,"landing_page_url":"https://doi.org/10.20944/preprints202610.3021.v1","pdf_url":null,"source":{"id":"https://openalex.org/S6309402219","display_name":"Preprints.org","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"posted-content"},"volume":null,"type":"preprint","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.20944/preprints202610.3021.v1","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101813639","display_name":"Mahmoud M. Taha","orcid":"https://orcid.org/0000-0002-9148-6960","observed_orcids":["https://orcid.org/0000-0002-9148-6960"]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Mahmoud M. Taha","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102008271","display_name":"Abdelrahman Ahmed","orcid":"https://orcid.org/0000-0001-9530-766X","observed_orcids":["https://orcid.org/0000-0001-9530-766X"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Abdelrahman Ahmed","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5140248671","display_name":"Abdelrahman Mohamed","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Abdelrahman Mohamed","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5012965279","display_name":"Fathy M. Mustafa","orcid":"https://orcid.org/0000-0001-5627-9061","observed_orcids":["https://orcid.org/0000-0001-5627-9061"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fathy M. Mustafa","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0001-5627-9061","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5101813639"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9193999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9193999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.03350000083446503,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.015699999406933784,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/edge-inference","display_name":"edge inference","score":0.9900000095367432},{"id":"https://openalex.org/keywords/c-extensions","display_name":"C language extension","score":0.5740000009536743},{"id":"https://openalex.org/keywords/systolic-arrays","display_name":"systolic arrays","score":0.824999988079071},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.3149999976158142},{"id":"https://openalex.org/keywords/low-power-embedded-processors","display_name":"low-power embedded processors","score":0.43799999356269836}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8044999837875366},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7289999723434448},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.5629000067710876},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.49549999833106995},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.490200012922287},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4896000027656555},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.46700000762939453},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44600000977516174},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42579999566078186},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3749000132083893},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.3716999888420105},{"id":"https://openalex.org/C52173422","wikidata":"https://www.wikidata.org/wiki/Q766483","display_name":"Opcode","level":2,"score":0.3707999885082245},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.36480000615119934},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3481999933719635},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.3255999982357025},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.31220000982284546},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.30720001459121704},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.3041999936103821},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.296099990606308},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.29429998993873596},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2833000123500824},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.2808000147342682},{"id":"https://openalex.org/C95623464","wikidata":"https://www.wikidata.org/wiki/Q1096149","display_name":"Classifier (UML)","level":2,"score":0.2782999873161316},{"id":"https://openalex.org/C157170001","wikidata":"https://www.wikidata.org/wiki/Q4781507","display_name":"Applications of artificial intelligence","level":2,"score":0.26969999074935913},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.26969999074935913},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.2655999958515167},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.25609999895095825}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.20944/preprints202610.3021.v1","doi":"https://doi.org/10.20944/preprints202610.3021.v1","is_oa":true,"landing_page_url":"https://doi.org/10.20944/preprints202610.3021.v1","pdf_url":null,"source":{"id":"https://openalex.org/S6309402219","display_name":"Preprints.org","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"posted-content"}],"best_oa_location":{"id":"doi:10.20944/preprints202610.3021.v1","doi":"https://doi.org/10.20944/preprints202610.3021.v1","is_oa":true,"landing_page_url":"https://doi.org/10.20944/preprints202610.3021.v1","pdf_url":null,"source":{"id":"https://openalex.org/S6309402219","display_name":"Preprints.org","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"posted-content"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5378999710083008}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W7204110445","https://openalex.org/W7105059900","https://openalex.org/W7140827467","https://openalex.org/W7211940265","https://openalex.org/W7220324851","https://openalex.org/W7138349853","https://openalex.org/W4416225884","https://openalex.org/W7106265163","https://openalex.org/W7221341904","https://openalex.org/W7169875884"],"abstract_inverted_index":{"Edge":[0],"AI":[1],"inference":[2,18,123,193],"on":[3,111,185],"resource-constrained":[4],"devices":[5],"demands":[6],"low":[7],"latency,":[8,24],"minimal":[9],"memory":[10],"footprint,":[11],"and":[12,26,51,71,137,208,217],"tight":[13],"power":[14],"budgets---requirements":[15],"that":[16,115,179],"cloud-based":[17],"cannot":[19],"satisfy":[20],"due":[21],"to":[22],"network":[23],"bandwidth,":[25],"privacy":[27],"costs.":[28],"This":[29],"paper":[30],"presents":[31],"the":[32,59,65,89,102,116,173,200,203],"design":[33],"of":[34,92,202],"an":[35,131],"RV32IMC":[36],"processor":[37,57],"tightly":[38,180],"coupled":[39],"with":[40,163],"a":[41,72,93,120,127,138,142,154,168,186],"custom":[42,98],"ISA-extended":[43],"linear-classifier":[44],"accelerator,":[45],"described":[46],"in":[47,101,124,172,214],"synthesizable":[48],"SystemVerilog":[49],"RTL":[50,109],"evaluated":[52],"through":[53],"cycle-accurate":[54],"simulation.":[55],"The":[56,150],"implements":[58],"RISC-V":[60,188,204],"RV32I":[61,144],"base":[62],"integer":[63],"set,":[64],"M":[66],"extension":[67,75,152],"for":[68,76,195],"hardware":[69,117],"multiply/divide,":[70],"partial":[73],"C":[74,151],"16-bit":[77],"compressed":[78],"instructions.":[79],"A":[80],"4\u00d74":[81],"weight-stationary":[82],"systolic":[83],"array":[84],"is":[85],"integrated":[86],"directly":[87],"into":[88],"execute":[90],"stage":[91],"five-stage":[94],"pipeline":[95],"via":[96,167],"four":[97],"instructions":[99],"encoded":[100],"reserved":[103],"custom-0":[104],"opcode":[105],"space":[106],"(0x0B).":[107],"Cycle-accurate":[108],"simulation":[110],"Vivado":[112],"xsim":[113],"shows":[114],"accelerator":[118],"completes":[119],"4-class":[121],"linear-classification":[122],"19":[125],"cycles,":[126],"4.2\u00d7":[128],"speedup":[129,140],"over":[130,141],"RV32IM":[132],"software":[133,146],"baseline":[134,147],"(79":[135],"cycles)":[136],"40.1\u00d7":[139],"realistic":[143],"general-purpose":[145],"(761":[148],"cycles).":[149],"delivers":[153],"24.24%":[155],"code-size":[156],"reduction":[157],"(528":[158],"B":[159],"\u2192":[160],"400":[161],"B)":[162],"zero":[164],"performance":[165],"penalty,":[166],"purely":[169],"combinational":[170],"decompressor":[171],"fetch":[174],"stage.":[175],"These":[176],"results":[177],"indicate":[178],"coupled,":[181],"domain-specific":[182],"ISA":[183],"extensions":[184],"compact":[187],"core":[189],"can":[190],"deliver":[191],"meaningful":[192],"acceleration":[194],"edge":[196],"deployment":[197],"while":[198],"preserving":[199],"modularity":[201],"ecosystem.":[205],"FPGA":[206],"synthesis":[207],"on-hardware":[209],"characterization":[210],"were":[211],"not":[212],"performed":[213],"this":[215],"work":[216],"are":[218],"identified":[219],"as":[220],"future":[221],"work.":[222]},"counts_by_year":[],"updated_date":"2026-11-01T11:40:01.658920","created_date":"2026-10-31T00:00:00"}
