{"id":"https://openalex.org/W7224134079","doi":"https://doi.org/10.48550/arxiv.2610.37530","title":"Back-End-Of-Line Integration of 2-Terminal Ferroelectric Hafnia Synaptic Weights on Commercial CMOS Process","display_name":"Back-End-Of-Line Integration of 2-Terminal Ferroelectric Hafnia Synaptic Weights on Commercial CMOS Process","publication_year":2026,"publication_date":"2026-10-27","ids":{"openalex":"https://openalex.org/W7224134079","doi":"https://doi.org/10.48550/arxiv.2610.37530"},"language":"en","primary_location":{"id":"pmh:oai:arXiv.org:2610.37530","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.37530","pdf_url":"https://arxiv.org/pdf/2610.37530","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"volume":null,"type":"preprint","is_traditional":true,"indexed_in":["arxiv","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2610.37530","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022445744","display_name":"Alexander Flasby","orcid":"https://orcid.org/0000-0002-1573-7537","observed_orcids":["https://orcid.org/0000-0002-1573-7537"]},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I4405253860","display_name":"Integrated Systems Laboratory","ror":"https://ror.org/015f9wa43","country_code":"CH","type":"facility","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088","https://openalex.org/I4405253860"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Flasby, Alexander","raw_affiliation_strings":["Integrated Systems Laboratory , ETH Zurich , Switzerland ,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory , ETH Zurich , Switzerland ,","institution_ids":["https://openalex.org/I35440088","https://openalex.org/I4405253860"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059763005","display_name":"Anwesha Panda","orcid":"https://orcid.org/0000-0001-7498-969X","observed_orcids":["https://orcid.org/0000-0001-7498-969X","https://orcid.org/0009-0000-5694-616X"]},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I4405253860","display_name":"Integrated Systems Laboratory","ror":"https://ror.org/015f9wa43","country_code":"CH","type":"facility","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088","https://openalex.org/I4405253860"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Panda, Anwesha","raw_affiliation_strings":["Integrated Systems Laboratory , ETH Zurich , Switzerland ,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory , ETH Zurich , Switzerland ,","institution_ids":["https://openalex.org/I35440088","https://openalex.org/I4405253860"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114285943","display_name":"Nathan Savoia","orcid":"https://orcid.org/0009-0006-7206-9236","observed_orcids":["https://orcid.org/0009-0006-7206-9236"]},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I4405253860","display_name":"Integrated Systems Laboratory","ror":"https://ror.org/015f9wa43","country_code":"CH","type":"facility","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088","https://openalex.org/I4405253860"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Savoia, Nathan","raw_affiliation_strings":["Integrated Systems Laboratory , ETH Zurich , Switzerland ,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory , ETH Zurich , Switzerland ,","institution_ids":["https://openalex.org/I35440088","https://openalex.org/I4405253860"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030684448","display_name":"Laura B\u00e9gon\u2010Lours","orcid":"https://orcid.org/0000-0003-2520-3317","observed_orcids":["https://orcid.org/0000-0003-2520-3317"]},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I4405253860","display_name":"Integrated Systems Laboratory","ror":"https://ror.org/015f9wa43","country_code":"CH","type":"facility","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088","https://openalex.org/I4405253860"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"B\u00e9gon-Lours, Laura","raw_affiliation_strings":["Integrated Systems Laboratory , ETH Zurich , Switzerland ,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory , ETH Zurich , Switzerland ,","institution_ids":["https://openalex.org/I35440088","https://openalex.org/I4405253860"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.6942999958992004,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.6942999958992004,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.3037000000476837,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.0003000000142492354,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/back-end-of-line-integration","display_name":"back-end-of-line integration","score":0.9470000267028809},{"id":"https://openalex.org/keywords/hafnium-oxide","display_name":"hafnium oxide","score":0.8999999761581421},{"id":"https://openalex.org/keywords/neuromorphic-hardware","display_name":"neuromorphic hardware","score":0.8119999766349792},{"id":"https://openalex.org/keywords/neural-network-accelerators","display_name":"neural network accelerators","score":0.8529999852180481},{"id":"https://openalex.org/keywords/on-device-learning","display_name":"on-device learning","score":0.6119999885559082},{"id":"https://openalex.org/keywords/thermal-budget","display_name":"thermal budget","score":0.8040000200271606},{"id":"https://openalex.org/keywords/0-18-mum-cmos","display_name":"0.18 \u03bcm CMOS","score":0.8069999814033508}],"concepts":[{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.7135999798774719},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.7089999914169312},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6539000272750854},{"id":"https://openalex.org/C66949984","wikidata":"https://www.wikidata.org/wiki/Q7662043","display_name":"Synaptic weight","level":3,"score":0.6495000123977661},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6245999932289124},{"id":"https://openalex.org/C79090758","wikidata":"https://www.wikidata.org/wiki/Q1045739","display_name":"Ferroelectricity","level":3,"score":0.5602999925613403},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.5297999978065491},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.5130000114440918},{"id":"https://openalex.org/C54725748","wikidata":"https://www.wikidata.org/wiki/Q7247277","display_name":"Process integration","level":2,"score":0.5065000057220459},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.47029998898506165},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.45730000734329224},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4090999960899353},{"id":"https://openalex.org/C525849907","wikidata":"https://www.wikidata.org/wiki/Q1096","display_name":"Tin","level":2,"score":0.3905999958515167},{"id":"https://openalex.org/C2776778127","wikidata":"https://www.wikidata.org/wiki/Q140736","display_name":"Hafnia","level":4,"score":0.38359999656677246},{"id":"https://openalex.org/C192157962","wikidata":"https://www.wikidata.org/wiki/Q4087243","display_name":"Bilayer","level":3,"score":0.37560001015663147},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.35350000858306885},{"id":"https://openalex.org/C57528182","wikidata":"https://www.wikidata.org/wiki/Q1271842","display_name":"Miniaturization","level":2,"score":0.3393999934196472},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3296000063419342},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.30630001425743103},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.289900004863739},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2849999964237213},{"id":"https://openalex.org/C141400236","wikidata":"https://www.wikidata.org/wiki/Q1479544","display_name":"Nanoelectronics","level":2,"score":0.2802000045776367},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.2800999879837036},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.27320000529289246},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26969999074935913},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.2612000107765198},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.26019999384880066},{"id":"https://openalex.org/C2777441419","wikidata":"https://www.wikidata.org/wiki/Q16969460","display_name":"Process window","level":3,"score":0.25870001316070557},{"id":"https://openalex.org/C204530211","wikidata":"https://www.wikidata.org/wiki/Q752823","display_name":"Thermal","level":2,"score":0.25099998712539673}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:arXiv.org:2610.37530","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.37530","pdf_url":"https://arxiv.org/pdf/2610.37530","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"doi:10.48550/arxiv.2610.37530","doi":"https://doi.org/10.48550/arxiv.2610.37530","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2610.37530","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2610.37530","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.37530","pdf_url":"https://arxiv.org/pdf/2610.37530","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"study_designs":[],"awards":[{"id":"https://openalex.org/G1603406322","display_name":"Ferroelectric Superlattices for Bio-Inspired Computing (ROSUBIO)","funder_award_id":"218438","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"},{"id":"https://openalex.org/G5697779717","display_name":null,"funder_award_id":"101194368","funder_id":"https://openalex.org/F4320334322","funder_display_name":"HORIZON EUROPE Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"},{"id":"https://openalex.org/F4320334322","display_name":"HORIZON EUROPE Framework Programme","ror":null}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7224134079.pdf","grobid_xml":"https://content.openalex.org/works/W7224134079.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4391635465","https://openalex.org/W6928726923","https://openalex.org/W4220706967","https://openalex.org/W3010984916","https://openalex.org/W2974354593","https://openalex.org/W7106521575","https://openalex.org/W3188859865","https://openalex.org/W7160514348","https://openalex.org/W7213247691","https://openalex.org/W4200296922"],"abstract_inverted_index":{"Functionalising":[0],"the":[1,26,29,37,95,103],"back-end-of-line":[2],"(BEOL)":[3],"of":[4,31,39],"CMOS":[5,44],"with":[6,76],"emerging":[7],"materials":[8],"is":[9,50,57,74,116],"a":[10,54,77],"key":[11],"route":[12],"to":[13],"neural":[14,120],"network":[15,121],"accelerators":[16],"and":[17,61,112],"neuromorphic":[18],"systems.":[19],"In":[20],"this":[21],"work,":[22],"we":[23],"demonstrate":[24],"for":[25],"first":[27],"time":[28],"integration":[30,105],"2-terminal":[32],"ferroelectric":[33],"synaptic":[34],"weights":[35,84],"in":[36,52],"BEOL":[38],"as-delivered":[40],"commercial":[41],"180":[42],"nm":[43],"dies.":[45],"A":[46],"novel":[47],"material":[48],"stack":[49],"proposed,":[51],"which":[53],"WOx/[HfO2-ZrO2]":[55],"bilayer":[56],"sandwiched":[58],"between":[59,109],"TiN":[60],"Mo":[62],"electrodes.":[63],"For":[64],"devices":[65],"annealed":[66,85],"at":[67,86],"450":[68],"\u00b0C,":[69],"programming":[70],"below":[71,80],"1.8":[72],"V":[73],"achieved":[75],"cycle-to-cycle":[78],"variation":[79],"3":[81],"%.":[82],"Synaptic":[83],"500":[87],"\u00b0C":[88],"exhibit":[89],"more":[90],"gradual":[91],"weight":[92],"updates,":[93],"while":[94],"tested":[96],"underlying":[97],"NMOS":[98],"transistors":[99],"remain":[100],"functional":[101],"after":[102],"complete":[104],"process.":[106],"The":[107],"trade-off":[108],"thermal":[110],"budget":[111],"on-device":[113],"training":[114],"performance":[115],"illustrated":[117],"using":[118],"hardware-aware":[119],"simulations.":[122]},"counts_by_year":[],"updated_date":"2026-11-06T12:05:46.655746","created_date":"2026-10-29T00:00:00"}
