{"id":"https://openalex.org/W7224089182","doi":"https://doi.org/10.48550/arxiv.2610.36481","title":"A State Augmented Approach to Paralle Modeling in High-Level Synthesis","display_name":"A State Augmented Approach to Paralle Modeling in High-Level Synthesis","publication_year":2026,"publication_date":"2026-10-27","ids":{"openalex":"https://openalex.org/W7224089182","doi":"https://doi.org/10.48550/arxiv.2610.36481"},"language":"en","primary_location":{"id":"pmh:oai:arXiv.org:2610.36481","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.36481","pdf_url":"https://arxiv.org/pdf/2610.36481","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"volume":null,"type":"preprint","is_traditional":true,"indexed_in":["arxiv","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2610.36481","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5160045058","display_name":"Nicholas Kovacs","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kovacs, Nicholas","raw_affiliation_strings":["University of South Florida Bellini College of Cybersecurity, AI, and Computing Tampa , Florida , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of South Florida Bellini College of Cybersecurity, AI, and Computing Tampa , Florida , USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5160043302","display_name":"Hao Zheng","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng, Hao","raw_affiliation_strings":["University of South Florida Bellini College of Cybersecurity, AI, and Computing Tampa , Florida , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of South Florida Bellini College of Cybersecurity, AI, and Computing Tampa , Florida , USA","institution_ids":["https://openalex.org/I2613432"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I2613432"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.9800000190734863},{"id":"https://openalex.org/keywords/architectural-modeling","display_name":"architectural modeling","score":0.6190000176429749},{"id":"https://openalex.org/keywords/state-augmentation","display_name":"state augmentation","score":0.5339999794960022},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.6050000190734863},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"instruction-level parallelism","score":0.5649999976158142}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7064999938011169},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.6148999929428101},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5849000215530396},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5828999876976013},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.5763999819755554},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4449000060558319},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4120999872684479},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.39500001072883606},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3846000134944916},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35589998960494995},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3517000079154968},{"id":"https://openalex.org/C49261128","wikidata":"https://www.wikidata.org/wiki/Q1132455","display_name":"Hazard","level":2,"score":0.34709998965263367},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.3409999907016754},{"id":"https://openalex.org/C84511453","wikidata":"https://www.wikidata.org/wiki/Q2914952","display_name":"Concurrency control","level":3,"score":0.3343000113964081},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.3285999894142151},{"id":"https://openalex.org/C2776834041","wikidata":"https://www.wikidata.org/wiki/Q25346349","display_name":"Execution model","level":2,"score":0.3116999864578247},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3091999888420105},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.30059999227523804},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2915000021457672},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.29100000858306885},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.290800005197525},{"id":"https://openalex.org/C12725497","wikidata":"https://www.wikidata.org/wiki/Q810247","display_name":"Baseline (sea)","level":2,"score":0.28929999470710754},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.2784999907016754},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.273499995470047},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.26739999651908875},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.2574999928474426},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2572000026702881},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.2551000118255615},{"id":"https://openalex.org/C12426560","wikidata":"https://www.wikidata.org/wiki/Q189569","display_name":"Basis (linear algebra)","level":2,"score":0.2531999945640564}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:arXiv.org:2610.36481","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.36481","pdf_url":"https://arxiv.org/pdf/2610.36481","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"doi:10.48550/arxiv.2610.36481","doi":"https://doi.org/10.48550/arxiv.2610.36481","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2610.36481","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2610.36481","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.36481","pdf_url":"https://arxiv.org/pdf/2610.36481","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7224089182.pdf","grobid_xml":"https://content.openalex.org/works/W7224089182.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2119299561","https://openalex.org/W4281926497","https://openalex.org/W7097014371","https://openalex.org/W7037753102","https://openalex.org/W2135448833","https://openalex.org/W7151768999","https://openalex.org/W1993273894","https://openalex.org/W7095558505","https://openalex.org/W3170941602","https://openalex.org/W4308090205"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"(HLS)":[2],"can":[3,21],"schedule":[4],"only":[5],"the":[6,23,110],"concurrency":[7],"made":[8],"legal":[9],"by":[10,143,147],"its":[11],"input":[12],"description.":[13],"For":[14],"feedback-coupled":[15],"designs,":[16],"a":[17,86,88,106,155,163],"sequential":[18,44],"behavioral":[19],"model":[20],"obscure":[22],"architectural":[24,38,98],"state":[25],"boundaries":[26],"and":[27,50,58,68,96,129,145,154,168],"hazard":[28],"resolution":[29],"needed":[30],"for":[31,124,134],"efficient":[32],"overlap.":[33],"We":[34],"develop":[35],"an":[36,125,135],"explicit":[37],"modeling":[39,81],"methodology":[40],"based":[41],"on":[42],"synchronous":[43],"processes":[45],"that":[46,72,94],"start":[47],"in":[48,63],"lockstep":[49],"synchronize":[51],"completion":[52],"before":[53],"repeating.":[54],"Persistent":[55],"state,":[56],"communication,":[57],"feedback":[59],"control":[60],"are":[61],"represented":[62],"C++,":[64],"while":[65],"HLS":[66,127],"schedules":[67],"binds":[69],"operations":[70],"within":[71],"structure.":[73],"A":[74],"five-stage":[75],"RV32I":[76],"processor":[77],"illustrates":[78],"three":[79],"consequential":[80],"decisions:":[82],"which":[83],"version":[84],"of":[85],"value":[87],"consumer":[89],"reads,":[90],"when":[91],"it":[92],"consumes":[93],"value,":[95],"how":[97],"memory":[99],"actions":[100],"map":[101],"to":[102],"port":[103],"operations.":[104],"On":[105],"Kintex":[107],"UltraScale+":[108],"FPGA,":[109],"CPI-optimized":[111],"configuration":[112,140],"achieves":[113],"1.221":[114],"cycles":[115,153],"per":[116],"instruction":[117],"at":[118,131],"220":[119],"MHz,":[120],"compared":[121],"with":[122,149],"4.000":[123],"algorithmic":[126],"baseline":[128],"1.575":[130],"242":[132],"MHz":[133,157],"Ibex":[136],"reference.":[137],"An":[138],"area-optimized":[139],"reduces":[141],"LUTs":[142],"65\\%":[144],"registers":[146],"47\\%,":[148],"9.7\\%":[150],"more":[151],"benchmark":[152],"250":[156],"achieved":[158],"clock.":[159],"These":[160],"results":[161],"demonstrate":[162],"separation":[164],"between":[165],"designer-controlled":[166],"architecture":[167],"tool-controlled":[169],"scheduling.":[170]},"counts_by_year":[],"updated_date":"2026-10-31T12:09:11.096373","created_date":"2026-10-29T00:00:00"}
