{"id":"https://openalex.org/W7220740253","doi":"https://doi.org/10.48550/arxiv.2610.05380","title":"VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation","display_name":"VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation","publication_year":2026,"publication_date":"2026-10-04","ids":{"openalex":"https://openalex.org/W7220740253","doi":"https://doi.org/10.48550/arxiv.2610.05380"},"language":"en","primary_location":{"id":"pmh:oai:arXiv.org:2610.05380","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.05380","pdf_url":"https://arxiv.org/pdf/2610.05380","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"volume":null,"type":"preprint","is_traditional":true,"indexed_in":["arxiv","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2610.05380","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000852169","display_name":"Prashanth Vijayaraghavan","orcid":"https://orcid.org/0009-0003-6370-9818","observed_orcids":["https://orcid.org/0009-0003-6370-9818"]},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijayaraghavan, Prashanth","raw_affiliation_strings":["IBM Research San Jose , CA , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Research San Jose , CA , USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035901172","display_name":"Akul Malhotra","orcid":"https://orcid.org/0000-0002-6152-2377","observed_orcids":["https://orcid.org/0000-0002-6152-2377"]},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malhotra, Akul","raw_affiliation_strings":["IBM Research San Jose , CA , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Research San Jose , CA , USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130060831","display_name":"Ashutosh Jadhav","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jadhav, Ashutosh","raw_affiliation_strings":["IBM Research San Jose , CA , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Research San Jose , CA , USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069189041","display_name":"Ehsan Degan","orcid":"https://orcid.org/0000-0002-6927-8719","observed_orcids":["https://orcid.org/0000-0002-6927-8719"]},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Degan, Ehsan","raw_affiliation_strings":["IBM Research San Jose , CA , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Research San Jose , CA , USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082917950","display_name":"Vandana V. Mukherjee","orcid":"https://orcid.org/0000-0002-8189-328X","observed_orcids":["https://orcid.org/0000-0002-8189-328X"]},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mukherjee, Vandana","raw_affiliation_strings":["IBM Research San Jose , CA , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Research San Jose , CA , USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5332000255584717,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5332000255584717,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10260","display_name":"Software Engineering Research","score":0.44040000438690186,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.004399999976158142,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.9620000123977661},{"id":"https://openalex.org/keywords/large-language-models","display_name":"large language models","score":0.9559999704360962},{"id":"https://openalex.org/keywords/benchmark","display_name":"benchmark","score":0.6959999799728394},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.6769999861717224},{"id":"https://openalex.org/keywords/test-bench","display_name":"test bench","score":0.7009999752044678},{"id":"https://openalex.org/keywords/functional-verification","display_name":"functional verification","score":0.8989999890327454},{"id":"https://openalex.org/keywords/hardware-design-automation","display_name":"hardware design automation","score":0.6349999904632568}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.9182000160217285},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8026000261306763},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7746999859809875},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.611299991607666},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5981000065803528},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5920000076293945},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.4779999852180481},{"id":"https://openalex.org/C19768560","wikidata":"https://www.wikidata.org/wiki/Q320727","display_name":"Dependency (UML)","level":2,"score":0.4239000082015991},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4140999913215637},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.4011000096797943},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3714999854564667},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3440999984741211},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30790001153945923},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.30379998683929443},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.2976999878883362},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.29249998927116394},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2754000127315521},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.2651999890804291},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2603999972343445},{"id":"https://openalex.org/C137293760","wikidata":"https://www.wikidata.org/wiki/Q3621696","display_name":"Language model","level":2,"score":0.25769999623298645},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.2565000057220459}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:arXiv.org:2610.05380","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.05380","pdf_url":"https://arxiv.org/pdf/2610.05380","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"doi:10.48550/arxiv.2610.05380","doi":"https://doi.org/10.48550/arxiv.2610.05380","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2610.05380","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2610.05380","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2610.05380","pdf_url":"https://arxiv.org/pdf/2610.05380","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7220740253.pdf","grobid_xml":"https://content.openalex.org/works/W7220740253.grobid-xml"},"referenced_works_count":10,"referenced_works":["https://openalex.org/W3177813494","https://openalex.org/W4386185625","https://openalex.org/W4387225871","https://openalex.org/W4389519225","https://openalex.org/W4403024178","https://openalex.org/W4405903187","https://openalex.org/W4413822481","https://openalex.org/W4415058512","https://openalex.org/W4415311429","https://openalex.org/W7084125780"],"related_works":["https://openalex.org/W7164836030","https://openalex.org/W7210263556","https://openalex.org/W7162632693","https://openalex.org/W7223206697","https://openalex.org/W7171513184","https://openalex.org/W4403023459","https://openalex.org/W7155609229","https://openalex.org/W7000456735","https://openalex.org/W4403024178","https://openalex.org/W4413144312"],"abstract_inverted_index":{"Large":[0],"Language":[1],"Models":[2],"(LLMs)":[3],"are":[4],"increasingly":[5],"applied":[6],"in":[7,14,37,144],"hardware":[8,18,167],"design":[9,65,148,168],"automation,":[10],"demonstrating":[11],"strong":[12],"potential":[13],"generating":[15],"and":[16,39,43,67,80,83,90,107,120,127,138,150,160,173],"understanding":[17],"description":[19],"languages.":[20],"However,":[21],"most":[22],"existing":[23],"benchmarks":[24],"focus":[25],"on":[26,62],"Verilog,":[27],"with":[28],"limited":[29],"evaluation":[30,97],"of":[31],"VHDL,":[32],"which":[33],"remains":[34],"widely":[35],"used":[36],"industry":[38],"academia":[40],"for":[41,58,165,177],"FPGA":[42],"safety-critical":[44],"systems.":[45],"To":[46],"address":[47],"this":[48],"gap,":[49],"we":[50],"introduce":[51],"VHDL-REPOBENCH,":[52],"a":[53,162],"large-scale,":[54],"cross-file,":[55],"repository-level":[56],"benchmark":[57,94,159],"assessing":[59],"LLM":[60,175],"capabilities":[61,176],"realistic":[63],"VHDL":[64,74,78,179],"generation":[66],"analysis":[68],"tasks.":[69],"VHDL-REPOBENCH":[70,153],"curates":[71],"~100":[72],"open-source":[73],"repositories,":[75],"encompassing":[76],"~2.5k":[77],"files":[79],"~500":[81],"testbenches,":[82],"provides":[84,161],"structured":[85],"problem":[86],"statements,":[87],"module":[88],"stubs,":[89],"self-verifying":[91],"testbenches.":[92],"The":[93],"enables":[95],"comprehensive":[96],"across":[98],"syntax,":[99],"semantic":[100],"correctness,":[101],"hierarchical":[102,147],"reasoning,":[103,146],"cross-file":[104],"dependency":[105],"resolution,":[106],"functional":[108],"verification.":[109],"We":[110],"evaluate":[111],"several":[112],"state-of-the-art":[113],"models,":[114],"including":[115],"GPT-4o,":[116],"Llama-3-70B,":[117],"Qwen2.5-72B,":[118],"CodeLlama-70B,":[119],"multi-step":[121],"reasoning":[122],"approaches":[123],"such":[124],"as":[125],"Reflexion":[126],"CoDes.":[128],"Results":[129],"reveal":[130],"that":[131],"while":[132],"current":[133],"LLMs":[134],"achieve":[135],"moderate":[136],"line-":[137],"block-level":[139],"accuracy,":[140],"substantial":[141],"challenges":[142],"remain":[143],"multi-file":[145],"understanding,":[149],"specification-to-module":[151],"generation.":[152],"represents":[154],"the":[155,166],"first":[156],"large-scale":[157],"VHDL-focused":[158],"valuable":[163],"resource":[164],"community":[169],"to":[170],"evaluate,":[171],"compare,":[172],"advance":[174],"practical":[178],"development.":[180]},"counts_by_year":[],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2026-10-07T00:00:00"}