{"id":"https://openalex.org/W7209945854","doi":null,"title":"Analog in-memory computing based on phase-change memory: programming algorithms and applications.","display_name":"Analog in-memory computing based on phase-change memory: programming algorithms and applications.","publication_year":2026,"publication_date":"2026-04-10","ids":{"openalex":"https://openalex.org/W7209945854"},"language":"en","primary_location":{"id":"pmh:oai:amsdottorato.cib.unibo.it:13138","doi":null,"is_oa":false,"landing_page_url":"https://amsdottorato.unibo.it/id/eprint/13138/1/PhD_Thesis_Francesco_zavalloni_Revisioned_final.pdf","pdf_url":"https://amsdottorato.unibo.it/id/eprint/13138/1/PhD_Thesis_Francesco_zavalloni_Revisioned_final.pdf","source":{"id":"https://openalex.org/S4306400630","display_name":"AMS Dottorato Institutional Doctoral Theses Repository (University of Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I9360294","host_organization_name":"University of Bologna","host_organization_lineage":["https://openalex.org/I9360294"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Doctoral Thesis"},"volume":null,"type":"dissertation","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065394768","display_name":"Francesco Zavalloni","orcid":"https://orcid.org/0000-0003-0103-8126","observed_orcids":["https://orcid.org/0000-0003-0103-8126"]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Zavalloni, Francesco <1994>","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5065394768"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11315","display_name":"Phase-change materials and chalcogenides","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2505","display_name":"Materials Chemistry"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analog-in-memory-computing","display_name":"analog in-memory computing","score":0.9779999852180481},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"phase-change memory","score":0.9990000128746033},{"id":"https://openalex.org/keywords/resistive-memory-devices","display_name":"resistive memory devices","score":0.8040000200271606},{"id":"https://openalex.org/keywords/conductance-drift","display_name":"conductance drift","score":0.7950000166893005},{"id":"https://openalex.org/keywords/randomness","display_name":"randomness","score":0.3610000014305115},{"id":"https://openalex.org/keywords/matrix-vector-multiplication","display_name":"matrix-vector multiplication","score":0.8349999785423279},{"id":"https://openalex.org/keywords/deep-neural-network-inference","display_name":"deep neural network inference","score":0.8489999771118164},{"id":"https://openalex.org/keywords/energy-efficient-computing","display_name":"energy-efficient computing","score":0.7229999899864197},{"id":"https://openalex.org/keywords/non-von-neumann-architecture","display_name":"non-von Neumann architecture","score":0.8799999952316284},{"id":"https://openalex.org/keywords/mnist-classification","display_name":"MNIST classification","score":0.9010000228881836},{"id":"https://openalex.org/keywords/motor-control","display_name":"motor control","score":0.6179999709129333},{"id":"https://openalex.org/keywords/hardware-characterization","display_name":"hardware characterization","score":0.382999986410141}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8159000277519226},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.5667999982833862},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5351999998092651},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.522599995136261},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.4837000072002411},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.48170000314712524},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.45329999923706055},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41679999232292175},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.40939998626708984},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3702000081539154},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.3422999978065491},{"id":"https://openalex.org/C2780971903","wikidata":"https://www.wikidata.org/wiki/Q2933705","display_name":"Stochastic computing","level":3,"score":0.325300008058548},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.311599999666214},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.30410000681877136},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3012000024318695},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.2858000099658966},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.28450000286102295},{"id":"https://openalex.org/C6899612","wikidata":"https://www.wikidata.org/wiki/Q852911","display_name":"Resistive touchscreen","level":2,"score":0.2827000021934509},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2791999876499176},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.2773999869823456},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.27250000834465027},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.26170000433921814},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.25920000672340393},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.2515999972820282}],"mesh":[],"locations_count":1,"locations":[{"id":"pmh:oai:amsdottorato.cib.unibo.it:13138","doi":null,"is_oa":false,"landing_page_url":"https://amsdottorato.unibo.it/id/eprint/13138/1/PhD_Thesis_Francesco_zavalloni_Revisioned_final.pdf","pdf_url":"https://amsdottorato.unibo.it/id/eprint/13138/1/PhD_Thesis_Francesco_zavalloni_Revisioned_final.pdf","source":{"id":"https://openalex.org/S4306400630","display_name":"AMS Dottorato Institutional Doctoral Theses Repository (University of Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I9360294","host_organization_name":"University of Bologna","host_organization_lineage":["https://openalex.org/I9360294"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Doctoral Thesis"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W7112025749","https://openalex.org/W6929486427","https://openalex.org/W4417441911","https://openalex.org/W4388145528","https://openalex.org/W4403059124","https://openalex.org/W7161117747","https://openalex.org/W4403105232","https://openalex.org/W4412442306","https://openalex.org/W7111557496","https://openalex.org/W7160378945"],"abstract_inverted_index":{"In":[0,222],"the":[1,23,28,84,119,136,183,200,245],"era":[2],"of":[3,27,73,83,122,185,217,227],"Artificial":[4],"Intelligence":[5],"(AI),":[6],"many":[7],"applications":[8,218],"demand":[9],"low-power":[10],"computation":[11,112],"over":[12,173],"large":[13],"datasets.":[14],"Conventional":[15],"digital":[16],"computers":[17],"face":[18],"performance":[19,256],"limitations":[20],"due":[21,145],"to":[22,92,146,243,290],"inherent":[24],"communication":[25],"bottleneck":[26],"Von":[29],"Neumann":[30,66],"architecture,":[31],"which":[32],"requires":[33],"frequent":[34],"data":[35],"transfers":[36],"between":[37],"memory":[38,60,116,123],"and":[39,70,106,125,132,153,175,189,219,236,248,271],"processing":[40],"units.":[41],"To":[42],"address":[43],"this":[44],"challenge,":[45],"novel":[46,205],"computational":[47],"paradigms":[48],"have":[49],"emerged.":[50],"Among":[51,135],"these,":[52],"Analog":[53],"In-Memory":[54],"Computing":[55],"(AIMC),":[56],"based":[57],"on":[58],"resistive":[59,115],"devices,":[61,210],"offers":[62],"a":[63,80,214,232,237,296],"promising":[64],"non-Von":[65],"approach":[67],"for":[68,208],"fast":[69],"energy-efficient":[71],"execution":[72],"matrix-vector":[74],"multiplications":[75],"(MVMs).":[76],"Since":[77],"MVMs":[78],"constitute":[79],"significant":[81,255],"portion":[82],"workload":[85],"in":[86,177],"deep":[87],"learning":[88],"inference,":[89],"AIMC\u2019s":[90],"ability":[91],"perform":[93],"these":[94],"operations":[95],"with":[96,155],"constant":[97],"time":[98],"complexity":[99],"(O(1))":[100],"can":[101],"substantially":[102],"enhance":[103],"both":[104],"speed":[105],"energy":[107],"efficiency.":[108],"AIMC":[109,287],"performs":[110],"analog":[111,187],"directly":[113],"within":[114],"by":[117,203,284],"leveraging":[118,285],"physical":[120],"properties":[121],"devices":[124,162],"fundamental":[126],"electrical":[127],"principles":[128],"such":[129,261],"as":[130,262],"Ohm\u2019s":[131],"Kirchhoff\u2019s":[133],"laws.":[134],"candidate":[137],"technologies,":[138],"Phase-Change":[139],"Memory":[140],"(PCM)":[141],"is":[142],"particularly":[143],"attractive":[144],"its":[147],"multi-bit":[148],"storage":[149],"capability,":[150],"long":[151],"retention,":[152],"compatibility":[154],"standard":[156],"CMOS":[157],"fabrication":[158],"processes.":[159],"However,":[160],"PCM":[161,209,293],"exhibit":[163],"unique":[164],"non-idealities,":[165],"including":[166],"non-linear":[167],"current-voltage":[168],"characteristics,":[169],"stochastic":[170],"conductance":[171],"drift":[172,246],"time,":[174],"variability":[176],"programmed":[178],"states.":[179],"These":[180,280],"factors":[181],"degrade":[182],"accuracy":[184,250],"PCM-based":[186],"accelerators":[188],"consequently":[190],"impact":[191],"overall":[192],"application-level":[193],"performance.":[194],"This":[195],"thesis":[196],"addresses":[197],"challenges":[198],"at":[199],"programming":[201,228,234,239],"level":[202],"proposing":[204],"multilevel":[206],"algorithm":[207,235],"validating":[211],"them":[212],"through":[213,274],"wide":[215],"range":[216],"hardware":[220,297],"characterization.":[221],"particular,":[223],"two":[224,286],"major":[225],"types":[226],"algorithms":[229],"are":[230],"addressed:":[231],"single-cell":[233],"dual-cell":[238],"algorithm.":[240],"Both":[241],"aim":[242],"minimize":[244],"effect":[247],"improve":[249],"using":[251],"various":[252],"strategies,":[253],"achieving":[254],"improvements":[257],"across":[258],"different":[259],"applications,":[260],"binary":[263],"pattern":[264],"matching":[265],"recognition,":[266],"motor":[267],"control":[268],"stability":[269],"preservation,":[270],"MNIST":[272],"classification":[273],"Deep":[275],"Neural":[276],"Network":[277],"(DNN)":[278],"inference.":[279],"aspects":[281],"were":[282],"studied":[283],"prototypes":[288],"designed":[289],"mitigate":[291],"some":[292],"non-idealities":[294],"from":[295],"perspective.":[298]},"counts_by_year":[],"updated_date":"2026-09-25T08:18:29.962427","created_date":"2026-09-06T00:00:00"}