{"id":"https://openalex.org/W7204804410","doi":"https://doi.org/10.48550/arxiv.2608.28076","title":"Performance Evaluation of Fast Fourier Transforms on Emerging RISC-V Hardware with Vector Extension Support","display_name":"Performance Evaluation of Fast Fourier Transforms on Emerging RISC-V Hardware with Vector Extension Support","publication_year":2026,"publication_date":"2026-08-28","ids":{"openalex":"https://openalex.org/W7204804410","doi":"https://doi.org/10.48550/arxiv.2608.28076"},"language":"en","primary_location":{"id":"pmh:oai:arXiv.org:2608.28076","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2608.28076","pdf_url":"https://arxiv.org/pdf/2608.28076","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"volume":null,"type":"preprint","indexed_in":["arxiv","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2608.28076","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037106531","display_name":"Daniel Seibel","orcid":"https://orcid.org/0000-0003-3833-2089","observed_orcids":["https://orcid.org/0000-0003-3833-2089"]},"institutions":[{"id":"https://openalex.org/I4405269544","display_name":"J\u00fclich Supercomputing Centre","ror":"https://ror.org/04g2j9721","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405269544"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Seibel, Daniel","raw_affiliation_strings":["J\u00fclich Supercomputing Centre , J\u00fclich , Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"J\u00fclich Supercomputing Centre , J\u00fclich , Germany","institution_ids":["https://openalex.org/I4405269544"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005592145","display_name":"Kaveh Haghighi Mood","orcid":"https://orcid.org/0000-0002-8578-4961","observed_orcids":["https://orcid.org/0000-0002-8578-4961"]},"institutions":[{"id":"https://openalex.org/I4405269544","display_name":"J\u00fclich Supercomputing Centre","ror":"https://ror.org/04g2j9721","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405269544"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mood, Kaveh Haghighi","raw_affiliation_strings":["J\u00fclich Supercomputing Centre , J\u00fclich , Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"J\u00fclich Supercomputing Centre , J\u00fclich , Germany","institution_ids":["https://openalex.org/I4405269544"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016325585","display_name":"Jayesh Badwaik","orcid":"https://orcid.org/0000-0002-5252-8179","observed_orcids":["https://orcid.org/0000-0002-5252-8179"]},"institutions":[{"id":"https://openalex.org/I4405269544","display_name":"J\u00fclich Supercomputing Centre","ror":"https://ror.org/04g2j9721","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405269544"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Badwaik, Jayesh","raw_affiliation_strings":["J\u00fclich Supercomputing Centre , J\u00fclich , Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"J\u00fclich Supercomputing Centre , J\u00fclich , Germany","institution_ids":["https://openalex.org/I4405269544"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030158519","display_name":"Prateek Chawla","orcid":"https://orcid.org/0000-0001-8895-2791","observed_orcids":["https://orcid.org/0000-0001-8895-2791"]},"institutions":[{"id":"https://openalex.org/I4405269544","display_name":"J\u00fclich Supercomputing Centre","ror":"https://ror.org/04g2j9721","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405269544"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Chawla, Prateek","raw_affiliation_strings":["J\u00fclich Supercomputing Centre , J\u00fclich , Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"J\u00fclich Supercomputing Centre , J\u00fclich , Germany","institution_ids":["https://openalex.org/I4405269544"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032158508","display_name":"Stepan Nassyr","orcid":"https://orcid.org/0000-0002-0035-244X","observed_orcids":["https://orcid.org/0000-0002-0035-244X"]},"institutions":[{"id":"https://openalex.org/I4405269544","display_name":"J\u00fclich Supercomputing Centre","ror":"https://ror.org/04g2j9721","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405269544"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Nassyr, Stepan","raw_affiliation_strings":["J\u00fclich Supercomputing Centre , J\u00fclich , Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"J\u00fclich Supercomputing Centre , J\u00fclich , Germany","institution_ids":["https://openalex.org/I4405269544"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5144086253","display_name":"Andreas Herten","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405269544","display_name":"J\u00fclich Supercomputing Centre","ror":"https://ror.org/04g2j9721","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4405269544"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Herten, Andreas","raw_affiliation_strings":["J\u00fclich Supercomputing Centre , J\u00fclich , Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"J\u00fclich Supercomputing Centre , J\u00fclich , Germany","institution_ids":["https://openalex.org/I4405269544"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4405269544"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.0031999999191612005,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.0020000000949949026,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"fast Fourier transform","score":0.921999990940094},{"id":"https://openalex.org/keywords/risc-v-vector-extension","display_name":"RISC-V vector extension","score":0.8769999742507935},{"id":"https://openalex.org/keywords/vectorization","display_name":"vectorization","score":0.7639999985694885}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7512000203132629},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7373999953269958},{"id":"https://openalex.org/C41681595","wikidata":"https://www.wikidata.org/wiki/Q7917855","display_name":"Vectorization (mathematics)","level":2,"score":0.6855999827384949},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.6370000243186951},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4790000021457672},{"id":"https://openalex.org/C57733114","wikidata":"https://www.wikidata.org/wiki/Q1006032","display_name":"Discrete Fourier transform (general)","level":5,"score":0.4699000120162964},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.46560001373291016},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.44929999113082886},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4489000141620636},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4260999858379364},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.40869998931884766},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37450000643730164},{"id":"https://openalex.org/C2780365336","wikidata":"https://www.wikidata.org/wiki/Q25047934","display_name":"Single-core","level":2,"score":0.3431999981403351},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.3264999985694885},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.32010000944137573},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.31189998984336853},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3093999922275543},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.30070000886917114},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2930999994277954},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.2890999913215637},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.2879999876022339},{"id":"https://openalex.org/C77928272","wikidata":"https://www.wikidata.org/wiki/Q7243214","display_name":"Prime-factor FFT algorithm","level":5,"score":0.27950000762939453},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2782000005245209},{"id":"https://openalex.org/C19118579","wikidata":"https://www.wikidata.org/wiki/Q786423","display_name":"Frequency domain","level":2,"score":0.27300000190734863},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2694000005722046},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2624000012874603},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.25690001249313354},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.25119999051094055}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:arXiv.org:2608.28076","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2608.28076","pdf_url":"https://arxiv.org/pdf/2608.28076","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"doi:10.48550/arxiv.2608.28076","doi":"https://doi.org/10.48550/arxiv.2608.28076","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2608.28076","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2608.28076","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2608.28076","pdf_url":"https://arxiv.org/pdf/2608.28076","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7204804410.pdf","grobid_xml":"https://content.openalex.org/works/W7204804410.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4386144808","https://openalex.org/W7214120056","https://openalex.org/W4387250977","https://openalex.org/W4416557585","https://openalex.org/W4307980119","https://openalex.org/W4416557617","https://openalex.org/W7102510782","https://openalex.org/W7204806167","https://openalex.org/W3153208734","https://openalex.org/W4293211458"],"abstract_inverted_index":{"This":[0],"manuscript":[1],"presents":[2],"a":[3,25,98],"performance":[4,76,114],"evaluation":[5],"of":[6,39,62,70,78,96,115],"Fast":[7],"Fourier":[8,31],"Transform":[9],"(FFT)":[10],"implementations":[11],"on":[12,46,51],"emerging":[13],"processors":[14],"supporting":[15],"the":[16,56,59,63,67,71,82,113],"RISC-V":[17,107],"Vector":[18],"Extension":[19],"(RVV":[20],"1.0).":[21],"By":[22],"introducing":[23],"juFFTe,":[24],"light-weight":[26],"high-performance":[27],"library":[28],"for":[29],"discrete":[30],"transforms,":[32],"it":[33],"is":[34],"demonstrated":[35],"how":[36],"effective":[37],"vectorization":[38],"performance-critical":[40],"FFT":[41],"kernels":[42],"can":[43],"be":[44],"achieved":[45],"RVV-enabled":[47,88],"hardware.":[48],"Comprehensive":[49],"benchmarks":[50],"three":[52],"RVV":[53],"1.0-ready":[54],"processors,":[55],"SiFive":[57],"X280,":[58],"X100":[60],"core":[61,69],"SpacemiT":[64],"K3":[65],"and":[66],"C920v2":[68],"Sophon":[72],"SG2044,":[73],"reveal":[74],"substantial":[75],"improvements":[77],"juFFTe":[79],"(https://github.com/FZJ-JSC/juFFTe)":[80],"over":[81],"widely":[83],"used":[84],"FFTW3":[85],"library.":[86],"Although":[87],"platforms":[89],"show":[90],"promising":[91],"results":[92],"at":[93],"this":[94],"stage":[95],"development,":[97],"comparison":[99],"with":[100],"AMD's":[101],"Zen":[102],"5":[103],"architecture":[104],"indicates":[105],"that":[106],"needs":[108],"further":[109],"maturing":[110],"to":[111],"reach":[112],"established":[116],"micro-architectures.":[117]},"counts_by_year":[],"updated_date":"2026-10-28T10:33:24.094632","created_date":"2026-09-01T00:00:00"}