{"id":"https://openalex.org/W7204476692","doi":"https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_13","title":"Btor2MLIR: A Format and Toolchain for Hardware Verification","display_name":"Btor2MLIR: A Format and Toolchain for Hardware Verification","publication_year":2023,"publication_date":"2023-09-16","ids":{"openalex":"https://openalex.org/W7204476692","doi":"https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_13"},"language":"en","primary_location":{"id":"pmh:oai:arXiv.org:2309.09100","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2309.09100","pdf_url":"https://arxiv.org/pdf/2309.09100","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"volume":null,"type":"preprint","is_traditional":true,"indexed_in":["arxiv","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2309.09100","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092905530","display_name":"Joseph Tafese","orcid":"https://orcid.org/0000-0002-4062-0592","observed_orcids":["https://orcid.org/0000-0002-4062-0592"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tafese, Joseph","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0002-4062-0592","affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046834577","display_name":"Arie Gurfinkel","orcid":"https://orcid.org/0000-0002-5964-6792","observed_orcids":["https://orcid.org/0000-0002-5964-6792"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Gurfinkel, Arie","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0002-5964-6792","affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5038035949","display_name":"Isabel Garcia-Contreras","orcid":"https://orcid.org/0000-0001-6098-3895","observed_orcids":["https://orcid.org/0000-0001-6098-3895"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Garcia-Contreras, Isabel","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0001-6098-3895","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9282000064849854,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9282000064849854,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.05169999971985817,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.014299999922513962,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-verification","display_name":"hardware verification","score":0.777999997138977},{"id":"https://openalex.org/keywords/hardware-model-checking","display_name":"hardware model checking","score":0.6930000185966492},{"id":"https://openalex.org/keywords/mlir","display_name":"MLIR","score":0.9190000295639038},{"id":"https://openalex.org/keywords/intermediate-representation","display_name":"intermediate representation","score":0.6650000214576721},{"id":"https://openalex.org/keywords/tool-chain","display_name":"toolchain","score":0.7599999904632568},{"id":"https://openalex.org/keywords/yosys","display_name":"Yosys","score":0.8059999942779541},{"id":"https://openalex.org/keywords/llvm","display_name":"LLVM","score":0.41100001335144043},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.3630000054836273}],"concepts":[{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.9035000205039978},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7742999792098999},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.6894999742507935},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5562999844551086},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5121999979019165},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.49790000915527344},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4722000062465668},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41990000009536743},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.41179999709129333},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.40470001101493835},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.38760000467300415},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.384799987077713},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.37929999828338623},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.37779998779296875},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37380000948905945},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3513000011444092},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.3474999964237213},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.33219999074935913},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.32850000262260437},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.3181999921798706},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.3179999887943268},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.29440000653266907},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.2906000018119812},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.28279998898506165},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.25589999556541443},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.25429999828338623},{"id":"https://openalex.org/C507366226","wikidata":"https://www.wikidata.org/wiki/Q42378","display_name":"USB","level":3,"score":0.25429999828338623}],"mesh":[],"locations_count":5,"locations":[{"id":"pmh:oai:arXiv.org:2309.09100","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2309.09100","pdf_url":"https://arxiv.org/pdf/2309.09100","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"pmh:doi:10.34727/2023/isbn.978-3-85448-060-0_13","doi":null,"is_oa":true,"landing_page_url":"http://hdl.handle.net/20.500.12708/188764","pdf_url":"https://repositum.tuwien.at/bitstream/20.500.12708/188764/1/Tafese-2023-Btor2MLIR%20A%20Format%20for%20Hardware%20Verification-vor.pdf","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Inproceedings"},{"id":"pmh:oai:repositum.tuwien.at:20.500.12708/188764","doi":null,"is_oa":true,"landing_page_url":"http://hdl.handle.net/20.500.12708/188764","pdf_url":null,"source":{"id":"https://openalex.org/S4306400493","display_name":"reposiTUm (TU Wien)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I145847075","host_organization_name":"TU Wien","host_organization_lineage":["https://openalex.org/I145847075"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design \u2013 FMCAD 2023","raw_type":"http://purl.org/coar/resource_type/c_5794"},{"id":"doi:10.48550/arxiv.2309.09100","doi":"https://doi.org/10.48550/arxiv.2309.09100","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2309.09100","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},{"id":"doi:10.34727/2023/isbn.978-3-85448-060-0_13","doi":"https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_13","is_oa":true,"landing_page_url":"https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_13","pdf_url":null,"source":{"id":"https://openalex.org/S4306400493","display_name":"reposiTUm (TU Wien)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I145847075","host_organization_name":"TU Wien","host_organization_lineage":["https://openalex.org/I145847075"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Other"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2309.09100","doi":null,"is_oa":true,"landing_page_url":"https://arxiv.org/abs/2309.09100","pdf_url":"https://arxiv.org/pdf/2309.09100","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7204476692.pdf","grobid_xml":"https://content.openalex.org/works/W7204476692.grobid-xml"},"referenced_works_count":2,"referenced_works":["https://openalex.org/W2097136089","https://openalex.org/W4212967627"],"related_works":["https://openalex.org/W4386875305","https://openalex.org/W2884110986","https://openalex.org/W6928926035","https://openalex.org/W4399036954","https://openalex.org/W6912068948","https://openalex.org/W6947662121","https://openalex.org/W4411260257","https://openalex.org/W4366451581","https://openalex.org/W4409360835","https://openalex.org/W4393942808"],"abstract_inverted_index":{"Formats":[0],"for":[1,10,33,148],"representing":[2,23],"and":[3,17,35,38,74,88,115,125,135,145],"manipulating":[4,34],"verification":[5,72,144],"problems":[6],"are":[7],"extremely":[8],"important":[9],"supporting":[11],"the":[12,42,45,52,58,64,94,133],"ecosystem":[13],"of":[14,27,47,100,122,128,143],"tools,":[15,73],"developers,":[16],"practitioners.":[18],"A":[19],"good":[20],"format":[21,60,87,134],"allows":[22],"many":[24],"different":[25],"types":[26],"problems,":[28,37],"has":[29,61],"a":[30,108,120],"strong":[31],"toolchain":[32],"translating":[36],"can":[39],"grow":[40],"with":[41],"community.":[43],"In":[44,80],"world":[46],"hardware":[48,149],"verification,":[49],"and,":[50],"specifically,":[51],"Hardware":[53],"Model":[54],"Checking":[55],"Competition":[56],"(HWMCC),":[57],"Btor2":[59],"emerged":[62],"as":[63],"dominating":[65],"format.":[66],"It":[67],"is":[68,102],"supported":[69],"by":[70],"Btor2Tools,":[71],"Verilog":[75],"design":[76],"tools":[77,147],"like":[78],"Yosys.":[79],"this":[81],"paper,":[82],"we":[83],"present":[84],"an":[85],"alternative":[86],"toolchain,":[89],"called":[90],"Btor2MLIR,":[91],"based":[92],"on":[93],"recent":[95],"MLIR":[96],"framework.":[97],"The":[98],"advantage":[99],"Btor2MLIR":[101],"in":[103],"reusing":[104],"existing":[105],"components":[106],"from":[107],"mature":[109],"compiler":[110],"infrastructure,":[111],"including":[112],"parsers,":[113],"text":[114],"binary":[116],"formats,":[117],"converters":[118],"to":[119,140],"variety":[121],"intermediate":[123],"representations,":[124],"executable":[126],"semantics":[127],"LLVM.":[129],"We":[130],"hope":[131],"that":[132],"our":[136],"tooling":[137],"will":[138],"lead":[139],"rapid":[141],"prototyping":[142],"related":[146],"verification.":[150]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3}],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2026-08-28T00:00:00"}
