{"id":"https://openalex.org/W7203470735","doi":"https://doi.org/10.1109/icdcece68961.2026.11646114","title":"Design of a Low Power Static Random Access Memory (SRAM) with Integration of Clock Gating Technique using 22nm of CMOS Technology","display_name":"Design of a Low Power Static Random Access Memory (SRAM) with Integration of Clock Gating Technique using 22nm of CMOS Technology","publication_year":2026,"publication_date":"2026-07-01","ids":{"openalex":"https://openalex.org/W7203470735","doi":"https://doi.org/10.1109/icdcece68961.2026.11646114"},"language":"en","primary_location":{"id":"doi:10.1109/icdcece68961.2026.11646114","doi":"https://doi.org/10.1109/icdcece68961.2026.11646114","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icdcece68961.2026.11646114","pdf_url":null,"source":{"id":"https://openalex.org/S7407088644","display_name":"International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/icdcece68961.2026.11646114","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5143525860","display_name":"P. Ranjithkumar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I83737708","display_name":"REVA University","ror":"https://ror.org/03gtcxd54","country_code":"IN","type":"education","lineage":["https://openalex.org/I83737708"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. Ranjithkumar","raw_affiliation_strings":["REVA University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"REVA University","institution_ids":["https://openalex.org/I83737708"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5147149753","display_name":"B Jarvis","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I83737708","display_name":"REVA University","ror":"https://ror.org/03gtcxd54","country_code":"IN","type":"education","lineage":["https://openalex.org/I83737708"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B Jarvis","raw_affiliation_strings":["REVA University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"REVA University","institution_ids":["https://openalex.org/I83737708"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022199502","display_name":"Prasenjit Deb","orcid":"https://orcid.org/0000-0002-6854-6654","observed_orcids":["https://orcid.org/0000-0002-6854-6654"]},"institutions":[{"id":"https://openalex.org/I83737708","display_name":"REVA University","ror":"https://ror.org/03gtcxd54","country_code":"IN","type":"education","lineage":["https://openalex.org/I83737708"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Prasenjit Deb","raw_affiliation_strings":["REVA University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"REVA University","institution_ids":["https://openalex.org/I83737708"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021009840","display_name":"M P Tejas","orcid":"https://orcid.org/0009-0007-9667-143X","observed_orcids":["https://orcid.org/0009-0007-9667-143X"]},"institutions":[{"id":"https://openalex.org/I83737708","display_name":"REVA University","ror":"https://ror.org/03gtcxd54","country_code":"IN","type":"education","lineage":["https://openalex.org/I83737708"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M P Tejas","raw_affiliation_strings":["REVA University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"REVA University","institution_ids":["https://openalex.org/I83737708"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I83737708"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sram","display_name":"SRAM","score":0.6710000038146973},{"id":"https://openalex.org/keywords/clock-gating","display_name":"clock gating","score":0.8560000061988831},{"id":"https://openalex.org/keywords/low-power-design","display_name":"low power design","score":0.8809999823570251},{"id":"https://openalex.org/keywords/6t-sram","display_name":"6T SRAM","score":0.9750000238418579},{"id":"https://openalex.org/keywords/d-flip-flop","display_name":"D flip-flop","score":0.9509999752044678},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.6010000109672546},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.9990000128746033},{"id":"https://openalex.org/keywords/22-nm-cmos","display_name":"22nm CMOS","score":0.9200000166893005},{"id":"https://openalex.org/keywords/energy-consumption-reduction","display_name":"energy consumption reduction","score":0.6959999799728394}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5934000015258789},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5726000070571899},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5478000044822693},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4884999990463257},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4555000066757202},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.4327999949455261},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.42969998717308044},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.37709999084472656},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.376800000667572},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3700000047683716},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3529999852180481},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3176000118255615},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3068000078201294},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2985000014305115},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2971000075340271},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.29190000891685486},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.28349998593330383},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.27570000290870667},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.27219998836517334},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.2705000042915344},{"id":"https://openalex.org/C3017773396","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Ultra low power","level":4,"score":0.25679999589920044},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25360000133514404},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.2535000145435333}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icdcece68961.2026.11646114","doi":"https://doi.org/10.1109/icdcece68961.2026.11646114","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icdcece68961.2026.11646114","pdf_url":null,"source":{"id":"https://openalex.org/S7407088644","display_name":"International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1109/icdcece68961.2026.11646114","doi":"https://doi.org/10.1109/icdcece68961.2026.11646114","is_oa":true,"landing_page_url":"https://doi.org/10.1109/icdcece68961.2026.11646114","pdf_url":null,"source":{"id":"https://openalex.org/S7407088644","display_name":"International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5378999710083008}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1994564481","https://openalex.org/W2076941902","https://openalex.org/W2519849818","https://openalex.org/W2534441289","https://openalex.org/W2548812458","https://openalex.org/W2593332647","https://openalex.org/W2783477863","https://openalex.org/W2902459906","https://openalex.org/W2907573123","https://openalex.org/W2949418755","https://openalex.org/W3009789205","https://openalex.org/W3016097573","https://openalex.org/W4363620538","https://openalex.org/W4378676127","https://openalex.org/W4409103638","https://openalex.org/W4411208096"],"related_works":["https://openalex.org/W2787658630","https://openalex.org/W4244306454","https://openalex.org/W3151951659","https://openalex.org/W4297897224","https://openalex.org/W1505038800","https://openalex.org/W3017807226","https://openalex.org/W7168178351","https://openalex.org/W3145981982","https://openalex.org/W1574514999","https://openalex.org/W7030094276"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,16,34],"evaluation":[4],"of":[5,38,98,104,115],"a":[6,12,47,64,68,96],"6T":[7],"SRAM":[8],"cell":[9],"design":[10,32,62],"utilizing":[11],"D":[13,65],"flip-flop":[14,66],"with":[15,67],"AND":[17,79],"gate-based":[18,70,80,93],"clock":[19,71,81,116],"gating":[20,72,82,117],"technique,":[21],"offering":[22],"superior":[23],"power":[24,36,85,108,122],"efficiency":[25],"compared":[26,50],"to":[27,51],"traditional":[28,58],"designs.":[29,124],"The":[30,78],"proposed":[31],"achieves":[33,95],"average":[35],"consumption":[37,86],"just":[39],"$\\mathbf{3":[40],"5":[41],"2.":[42],"9":[43],"2":[44],"n":[45],"W}$,":[46],"remarkable":[48],"reduction":[49,97],"the":[52,61,91,101,113],"$112.90":[53],"\\mu":[54,76],"\\mathrm{~W}$":[55],"consumed":[56],"by":[57,87],"circuits.":[59],"Additionally,":[60],"using":[63],"NAND":[69,92],"technique":[73],"consumes":[74],"$576.55":[75],"\\mathrm{~W}$.":[77],"Mechanism":[83],"optimizes":[84],"approximately":[88],"99.687%,":[89],"while":[90],"version":[94],"99.489%,":[99],"highlighting":[100],"substantial":[102],"impact":[103],"these":[105],"techniques":[106,118],"on":[107],"efficiency.":[109],"These":[110],"results":[111],"emphasize":[112],"potential":[114],"in":[119],"advancing":[120],"low":[121],"circuit":[123]},"counts_by_year":[],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2026-08-15T00:00:00"}
