{"id":"https://openalex.org/W7202009803","doi":null,"title":"Heterogeneous RISC-V based System-on-Chips for embedded computing platforms","display_name":"Heterogeneous RISC-V based System-on-Chips for embedded computing platforms","publication_year":2026,"publication_date":"2026-03-27","ids":{"openalex":"https://openalex.org/W7202009803"},"language":"en","primary_location":{"id":"pmh:oai:amsdottorato.cib.unibo.it:12839","doi":null,"is_oa":false,"landing_page_url":"https://amsdottorato.unibo.it/id/eprint/12839/1/sinigaglia_mattia_tesi.pdf","pdf_url":"https://amsdottorato.unibo.it/id/eprint/12839/1/sinigaglia_mattia_tesi.pdf","source":{"id":"https://openalex.org/S4306400630","display_name":"AMS Dottorato Institutional Doctoral Theses Repository (University of Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I9360294","host_organization_name":"University of Bologna","host_organization_lineage":["https://openalex.org/I9360294"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Doctoral Thesis"},"volume":null,"type":"dissertation","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069337658","display_name":"M. Sinigaglia","orcid":"https://orcid.org/0000-0002-3350-8789","observed_orcids":["https://orcid.org/0000-0002-3350-8789"]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Sinigaglia, Mattia <1993>","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5069337658"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/heterogeneous-system-on-chip","display_name":"heterogeneous system-on-chip","score":0.8230000138282776},{"id":"https://openalex.org/keywords/risc-v","display_name":"RISC-V","score":0.9919999837875366},{"id":"https://openalex.org/keywords/edge-computing","display_name":"edge computing","score":0.8859999775886536},{"id":"https://openalex.org/keywords/embedded-devices","display_name":"embedded devices","score":0.6039999723434448},{"id":"https://openalex.org/keywords/hardware-accelerators","display_name":"hardware accelerators","score":0.7390000224113464},{"id":"https://openalex.org/keywords/vector-processing","display_name":"vector processing","score":0.5320000052452087},{"id":"https://openalex.org/keywords/frequency-domain-signal-processing","display_name":"frequency-domain signal processing","score":0.6740000247955322},{"id":"https://openalex.org/keywords/wearable-ultrasound","display_name":"wearable ultrasound","score":0.5509999990463257},{"id":"https://openalex.org/keywords/cryptographic-hardware","display_name":"cryptographic hardware","score":0.7129999995231628},{"id":"https://openalex.org/keywords/root-of-trust","display_name":"root of trust","score":0.9440000057220459},{"id":"https://openalex.org/keywords/nano-drones","display_name":"nano-drones","score":0.8159999847412109},{"id":"https://openalex.org/keywords/autonomous-navigation","display_name":"autonomous navigation","score":0.6959999799728394},{"id":"https://openalex.org/keywords/hardware-software-co-design","display_name":"hardware-software co-design","score":0.8379999995231628},{"id":"https://openalex.org/keywords/energy-efficient-computing","display_name":"energy-efficient computing","score":0.45100000500679016},{"id":"https://openalex.org/keywords/shared-memory","display_name":"shared memory","score":0.5329999923706055},{"id":"https://openalex.org/keywords/audio-signal-processing","display_name":"audio signal processing","score":0.5350000262260437}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7932999730110168},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5705999732017517},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.48190000653266907},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4767000079154968},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4440000057220459},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.43380001187324524},{"id":"https://openalex.org/C138236772","wikidata":"https://www.wikidata.org/wiki/Q25098575","display_name":"Edge device","level":3,"score":0.42559999227523804},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4223000109195709},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4189999997615814},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4108999967575073},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3955000042915344},{"id":"https://openalex.org/C150594956","wikidata":"https://www.wikidata.org/wiki/Q1334829","display_name":"Wearable computer","level":2,"score":0.3379000127315521},{"id":"https://openalex.org/C2778456923","wikidata":"https://www.wikidata.org/wiki/Q5337692","display_name":"Edge computing","level":3,"score":0.33500000834465027},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32030001282691956},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.31839999556541443},{"id":"https://openalex.org/C54290928","wikidata":"https://www.wikidata.org/wiki/Q4845080","display_name":"Wearable technology","level":3,"score":0.3174000084400177},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.3131999969482422},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30889999866485596},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2937000095844269},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.2806999981403351},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2782000005245209},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.2770000100135803},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.2757999897003174},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2709999978542328},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.25679999589920044},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.25279998779296875},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.25209999084472656}],"mesh":[],"locations_count":1,"locations":[{"id":"pmh:oai:amsdottorato.cib.unibo.it:12839","doi":null,"is_oa":false,"landing_page_url":"https://amsdottorato.unibo.it/id/eprint/12839/1/sinigaglia_mattia_tesi.pdf","pdf_url":"https://amsdottorato.unibo.it/id/eprint/12839/1/sinigaglia_mattia_tesi.pdf","source":{"id":"https://openalex.org/S4306400630","display_name":"AMS Dottorato Institutional Doctoral Theses Repository (University of Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I9360294","host_organization_name":"University of Bologna","host_organization_lineage":["https://openalex.org/I9360294"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Doctoral Thesis"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4943999946117401,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W7204514615","https://openalex.org/W4403279662","https://openalex.org/W4361265333","https://openalex.org/W7139779798","https://openalex.org/W3211076556","https://openalex.org/W4384833578","https://openalex.org/W4281790130","https://openalex.org/W7214124090","https://openalex.org/W4401568785","https://openalex.org/W4411687695"],"abstract_inverted_index":{"Modern":[0],"embedded":[1,119],"devices":[2,120],"must":[3],"sense,":[4],"interpret,":[5],"and":[6,14,26,37,50,61,84,105,113,176,193,201,220,237,269,274,285],"act":[7],"on":[8],"the":[9,18,41,48,55,155],"edge":[10,79],"within":[11,278],"tight":[12],"power":[13],"size":[15],"budgets.":[16],"Closing":[17],"loop":[19],"locally":[20],"demands":[21],"low":[22,182],"latency,":[23],"predictable":[24],"timing,":[25],"robust":[27],"operation":[28],"from":[29,267],"sensors":[30],"through":[31,102,243],"control.":[32],"In":[33,76],"these":[34,250],"nodes,":[35],"moving":[36],"converting":[38],"data":[39,52,248],"is":[40],"dominant":[42],"cost,":[43],"so":[44],"placing":[45],"compute":[46],"near":[47,154],"source":[49],"minimizing":[51],"exchange":[53],"delivers":[54],"largest":[56],"gains.":[57],"Because":[58],"power,":[59],"interfaces,":[60],"form-factor":[62,144],"requirements":[63],"differ":[64],"among":[65],"device":[66],"classes,":[67],"a":[68,131,135,160,164,187,216,224,231],"single":[69],"uniform":[70],"architecture":[71],"cannot":[72],"meet":[73],"all":[74,277],"needs.":[75],"contrast,":[77],"effective":[78],"platforms":[80],"co-design":[81,104],"compute,":[82],"memory,":[83],"I/O":[85],"as":[86],"heterogeneous":[87],"System-on-Chips":[88],"(SoCs)":[89],"that":[90],"pair":[91],"general-purpose":[92,132,161,188,211],"processors":[93],"with":[94,99,134,163,181,190,215,230,282],"task-tuned":[95],"accelerators,":[96],"combining":[97],"flexibility":[98],"superior":[100],"energy\u2013performance":[101],"hardware\u2013software":[103],"system-level":[106],"validation.":[107],"This":[108],"thesis":[109],"addresses":[110],"this":[111],"challenge":[112],"proposes":[114],"four":[115],"silicon-proven":[116],"SoCs":[117],"for":[118,240,264],"in":[121,203],"an":[122],"intentional":[123],"progression":[124],"of":[125,138,227],"on-chip":[126],"heterogeneity.":[127],"First,":[128],"Buckbeak":[129],"pairs":[130],"core":[133,162,189],"reconfigurable":[136],"cluster":[137],"two":[139],"vector":[140],"engines,":[141],"adapting":[142],"their":[143],"execution":[145],"at":[146],"runtime":[147],"to":[148,170,179,196,246,257,272],"enable":[149],"efficient":[150],"mixed":[151],"scalar\u2013vector":[152],"workloads":[153],"sensor.":[156],"Next,":[157],"Echoes":[158],"augments":[159],"frequency-domain":[165,192],"Fast":[166],"Fourier":[167],"Transform":[168],"accelerator":[169,219],"process":[171],"multi-channel":[172],"digital":[173],"audio":[174,268],"interface":[175],"convert":[177],"streams":[178],"spectra":[180],"overhead.":[183],"Then,":[184],"Maestro":[185],"combines":[186],"both":[191],"vector\u2013tensor":[194],"engines":[195],"support":[197],"end-to-end":[198],"signal":[199],"processing":[200,212,263],"learning":[202],"wearable":[204],"ultrasound.":[205],"Finally,":[206],"AlSaqr":[207],"integrates":[208],"eight":[209],"parallel":[210],"cores":[213],"coupled":[214],"low-precision":[217],"tensor":[218],"cryptographic":[221],"units":[222],"under":[223],"hardware":[225],"Root":[226],"Trust":[228],"along":[229],"dual-core":[232],"Linux-capable":[233],"host,":[234],"enabling":[235],"secure":[236],"autonomous":[238],"navigation":[239],"nano-drones.":[241],"Coupled":[242],"shared":[244],"memories":[245],"minimize":[247],"movement,":[249],"complementary":[251],"approaches":[252],"demonstrate":[253],"how":[254],"tailoring":[255],"heterogeneity":[256],"domain":[258],"needs":[259],"can":[260],"sustain":[261],"on-device":[262],"applications":[265],"ranging":[266],"ultrasound":[270],"wearables":[271],"drones":[273],"robotics":[275],"systems,":[276],"ultra-low-power":[279],"envelopes":[280],"compatible":[281],"small":[283],"batteries":[284],"compact":[286],"form":[287],"factors.":[288]},"counts_by_year":[],"updated_date":"2026-09-25T08:18:29.962427","created_date":"2026-08-09T00:00:00"}