{"id":"https://openalex.org/W7161121981","doi":"https://doi.org/10.47191/etj/v11i05.11","title":"Logic Gates: Design Principles, Operational Analysis, And Applications in Digital Systems","display_name":"Logic Gates: Design Principles, Operational Analysis, And Applications in Digital Systems","publication_year":2026,"publication_date":"2026-05-14","ids":{"openalex":"https://openalex.org/W7161121981","doi":"https://doi.org/10.47191/etj/v11i05.11"},"language":"en","primary_location":{"id":"doi:10.47191/etj/v11i05.11","doi":"https://doi.org/10.47191/etj/v11i05.11","is_oa":true,"landing_page_url":"https://doi.org/10.47191/etj/v11i05.11","pdf_url":"https://everant.org/index.php/etj/article/download/2728/1997","source":{"id":"https://openalex.org/S4210237061","display_name":"Engineering and Technology Journal","issn_l":"2456-3358","issn":["2456-3358"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Engineering and Technology Journal","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://everant.org/index.php/etj/article/download/2728/1997","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039900313","display_name":"Aruna M Jarju","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I159098566","display_name":"Monroe University","ror":"https://ror.org/02sz42a76","country_code":"US","type":"education","lineage":["https://openalex.org/I159098566"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dr. Aruna M. Jarju","raw_affiliation_strings":["King Graduate School of Computer Science, Monroe University, New Rochelle, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"King Graduate School of Computer Science, Monroe University, New Rochelle, NY, USA","institution_ids":["https://openalex.org/I159098566"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5134311215","display_name":"Sahar Bukhari","orcid":"https://orcid.org/0000-0002-7490-3179","observed_orcids":["https://orcid.org/0000-0002-7490-3179"]},"institutions":[{"id":"https://openalex.org/I159098566","display_name":"Monroe University","ror":"https://ror.org/02sz42a76","country_code":"US","type":"education","lineage":["https://openalex.org/I159098566"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sahar Bukhari","raw_affiliation_strings":["King Graduate School of Computer Science, Monroe University, New Rochelle, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"King Graduate School of Computer Science, Monroe University, New Rochelle, NY, USA","institution_ids":["https://openalex.org/I159098566"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I159098566"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":"05","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12899","display_name":"Engineering and Technology Innovations","score":0.6664999723434448,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12899","display_name":"Engineering and Technology Innovations","score":0.6664999723434448,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.1526000052690506,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.07400000095367432,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gates","display_name":"logic gates","score":1.0},{"id":"https://openalex.org/keywords/boolean-algebra","display_name":"Boolean algebra","score":0.9779999852180481},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.8700000047683716},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":1.0},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.9909999966621399},{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.996999979019165},{"id":"https://openalex.org/keywords/universal-gates","display_name":"universal gates","score":0.8539999723434448},{"id":"https://openalex.org/keywords/truth-tables","display_name":"truth tables","score":0.8889999985694885},{"id":"https://openalex.org/keywords/boolean-formulas","display_name":"Boolean formulas","score":0.6600000262260437},{"id":"https://openalex.org/keywords/combinational-circuits","display_name":"combinational circuits","score":0.8669999837875366},{"id":"https://openalex.org/keywords/sequential-circuits","display_name":"sequential circuits","score":0.9980000257492065},{"id":"https://openalex.org/keywords/logic-design","display_name":"digital circuit design","score":0.8539999723434448},{"id":"https://openalex.org/keywords/binary-logic","display_name":"binary logic","score":0.7459999918937683},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"digital electronics","score":0.42399999499320984}],"concepts":[{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.7822999954223633},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6477000117301941},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6347000002861023},{"id":"https://openalex.org/C56949724","wikidata":"https://www.wikidata.org/wiki/Q219079","display_name":"Truth table","level":2,"score":0.5688999891281128},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5527999997138977},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5026999711990356},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4722999930381775},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4577000141143799},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4375999867916107},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.423799991607666},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4214000105857849},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.41449999809265137},{"id":"https://openalex.org/C196836630","wikidata":"https://www.wikidata.org/wiki/Q4753279","display_name":"And-inverter graph","level":4,"score":0.4066999852657318},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.40549999475479126},{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.38609999418258667},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.3853999972343445},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37540000677108765},{"id":"https://openalex.org/C39685927","wikidata":"https://www.wikidata.org/wiki/Q173183","display_name":"Boolean algebra","level":2,"score":0.36980000138282776},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.3573000133037567},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.35600000619888306},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.3481000065803528},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.3441999852657318},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.32420000433921814},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.3118000030517578},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.30959999561309814},{"id":"https://openalex.org/C188434589","wikidata":"https://www.wikidata.org/wiki/Q1478762","display_name":"Logic analyzer","level":3,"score":0.3037000000476837},{"id":"https://openalex.org/C21847791","wikidata":"https://www.wikidata.org/wiki/Q191081","display_name":"Logical conjunction","level":2,"score":0.29339998960494995},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2842999994754791},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.2754000127315521},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.26669999957084656},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2614000141620636},{"id":"https://openalex.org/C74992188","wikidata":"https://www.wikidata.org/wiki/Q239179","display_name":"Non-classical logic","level":3,"score":0.25760000944137573},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.2574000060558319},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2506999969482422}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.47191/etj/v11i05.11","doi":"https://doi.org/10.47191/etj/v11i05.11","is_oa":true,"landing_page_url":"https://doi.org/10.47191/etj/v11i05.11","pdf_url":"https://everant.org/index.php/etj/article/download/2728/1997","source":{"id":"https://openalex.org/S4210237061","display_name":"Engineering and Technology Journal","issn_l":"2456-3358","issn":["2456-3358"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Engineering and Technology Journal","raw_type":"journal-article"},{"id":"doi:10.5281/zenodo.20132197","doi":"https://doi.org/10.5281/zenodo.20132197","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.20132197","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"JournalArticle"},{"id":"doi:10.5281/zenodo.20132198","doi":"https://doi.org/10.5281/zenodo.20132198","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.20132198","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"JournalArticle"}],"best_oa_location":{"id":"doi:10.47191/etj/v11i05.11","doi":"https://doi.org/10.47191/etj/v11i05.11","is_oa":true,"landing_page_url":"https://doi.org/10.47191/etj/v11i05.11","pdf_url":"https://everant.org/index.php/etj/article/download/2728/1997","source":{"id":"https://openalex.org/S4210237061","display_name":"Engineering and Technology Journal","issn_l":"2456-3358","issn":["2456-3358"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Engineering and Technology Journal","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7161121981.pdf","grobid_xml":"https://content.openalex.org/works/W7161121981.grobid-xml"},"referenced_works_count":1,"referenced_works":["https://openalex.org/W2053619330"],"related_works":["https://openalex.org/W4390713300","https://openalex.org/W3009426035","https://openalex.org/W7027310878","https://openalex.org/W3185726547","https://openalex.org/W4385746906","https://openalex.org/W7202074182","https://openalex.org/W2913530739","https://openalex.org/W4386294748","https://openalex.org/W4249178015","https://openalex.org/W4388204532"],"abstract_inverted_index":{"Logic":[0,47],"gates":[1,39,48,102,115,157,172,205,244],"are":[2,127,143,186,214],"the":[3,14,56,99,132,150,153,168],"fundamental":[4],"building":[5],"blocks":[6],"of":[7,16,83,134,155,170,203,220,242],"all":[8],"digital":[9,23,146,164,230,251],"electronic":[10],"systems":[11,191],"and":[12,19,33,43,59,61,80,93,107,113,120,124,137,158,175,198,211,227,232,239,245],"form":[13],"basis":[15],"modern":[17,250],"computing":[18],"communication":[20,208],"technologies.":[21],"Every":[22],"device,":[24],"ranging":[25],"from":[26],"simple":[27,183],"calculators":[28],"to":[29,40,68,129,138,180,188,224],"complex":[30,190],"computers,":[31],"smartphones,":[32],"embedded":[34,212],"systems,":[35,209],"relies":[36],"on":[37,50,87],"logic":[38,84,101,171,204,243],"process,":[41],"store,":[42],"transmit":[44],"binary":[45,51,65],"information.":[46],"operate":[49],"inputs,":[52],"typically":[53],"represented":[54],"by":[55,72],"values":[57],"0":[58],"1,":[60],"generate":[62],"a":[63,78,236],"corresponding":[64],"output":[66],"according":[67],"logical":[69,141,184],"rules":[70],"defined":[71],"Boolean":[73,125],"algebra.":[74],"This":[75],"paper":[76,151],"presents":[77],"detailed":[79],"comprehensive":[81],"study":[82,97,222],"gates,":[85],"focusing":[86],"their":[88,160,246],"definitions,":[89],"classifications,":[90],"operating":[91],"principles,":[92],"mathematical":[94],"representations.":[95],"The":[96,217],"examines":[98],"basic":[100],"such":[103,192],"as":[104,109,111,193],"AND,":[105],"OR,":[106],"NOT,":[108],"well":[110],"derived":[112],"universal":[114,156],"including":[116],"NAND,":[117],"NOR,":[118],"XOR,":[119],"XNOR.":[121],"Truth":[122],"tables":[123],"expressions":[126],"used":[128],"clearly":[130],"explain":[131],"behavior":[133],"each":[135],"gate":[136],"demonstrate":[139],"how":[140,182],"operations":[142,185],"performed":[144],"within":[145],"circuits.":[147],"In":[148],"addition,":[149],"discusses":[152],"concept":[154],"explains":[159],"significance":[161],"in":[162,173,206,229,249],"simplifying":[163],"circuit":[165],"design.":[166,253],"Furthermore,":[167],"role":[169,248],"combinational":[174],"sequential":[176],"circuits":[177],"is":[178,223],"explored":[179],"illustrate":[181],"combined":[187],"build":[189],"adders,":[194],"memory":[195],"units,":[196],"processors,":[197],"control":[199],"systems.":[200],"Real-world":[201],"applications":[202],"computing,":[207],"automation,":[210],"technologies":[213],"also":[215],"highlighted.":[216],"primary":[218],"objective":[219],"this":[221],"provide":[225],"students":[226],"beginners":[228],"electronics":[231],"computer":[233],"science":[234],"with":[235],"clear,":[237],"structured,":[238],"in-depth":[240],"understanding":[241],"critical":[247],"system":[252]},"counts_by_year":[],"updated_date":"2026-11-05T12:25:35.769452","created_date":"2026-05-15T00:00:00"}