{"id":"https://openalex.org/W7147210941","doi":"https://doi.org/10.5281/zenodo.19357384","title":"Design And Analasys Of 8-Bit Multiplier For Low Power Vlsi Applications","display_name":"Design And Analasys Of 8-Bit Multiplier For Low Power Vlsi Applications","publication_year":2026,"publication_date":"2026-03-31","ids":{"openalex":"https://openalex.org/W7147210941","doi":"https://doi.org/10.5281/zenodo.19357384"},"language":"en","primary_location":{"id":"doi:10.5281/zenodo.19357384","doi":"https://doi.org/10.5281/zenodo.19357384","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.19357384","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article-journal"},"volume":null,"type":"article","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.5281/zenodo.19357384","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5132652668","display_name":"IJAENE","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"IJAENE","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5132652668"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15155552,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/8-bit-multiplier","display_name":"8-bit multiplier","score":0.9940000176429749},{"id":"https://openalex.org/keywords/low-power-arithmetic-circuits","display_name":"low-power arithmetic circuits","score":0.7839999794960022},{"id":"https://openalex.org/keywords/vlsi-design","display_name":"VLSI design","score":0.765999972820282},{"id":"https://openalex.org/keywords/partial-product-generation","display_name":"partial product generation","score":0.9779999852180481},{"id":"https://openalex.org/keywords/switching-activity-reduction","display_name":"switching activity reduction","score":0.7070000171661377},{"id":"https://openalex.org/keywords/dynamic-power-dissipation","display_name":"dynamic power dissipation","score":0.8270000219345093},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"propagation delay","score":0.8669999837875366},{"id":"https://openalex.org/keywords/area-utilization","display_name":"area utilization","score":0.6620000004768372},{"id":"https://openalex.org/keywords/energy-efficient-embedded-systems","display_name":"energy-efficient embedded systems","score":0.5690000057220459}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8195000290870667},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7789000272750854},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.567300021648407},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.541100025177002},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4756999909877777},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4602000117301941},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.45210000872612},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.43320000171661377},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.40119999647140503},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.39590001106262207},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.36329999566078186},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3603000044822693},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.359499990940094},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.35899999737739563},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3553999960422516},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.328900009393692},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3208000063896179},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3181999921798706},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.3174000084400177},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.3086000084877014},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.305400013923645},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.3000999987125397},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.2964000105857849},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29420000314712524},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2800999879837036},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.27549999952316284},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.27399998903274536},{"id":"https://openalex.org/C118993495","wikidata":"https://www.wikidata.org/wiki/Q5042828","display_name":"Electrical efficiency","level":3,"score":0.2648000121116638},{"id":"https://openalex.org/C3017773396","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Ultra low power","level":4,"score":0.26260000467300415},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.250900000333786}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.5281/zenodo.19357384","doi":"https://doi.org/10.5281/zenodo.19357384","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.19357384","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"},{"id":"doi:10.5281/zenodo.19357385","doi":"https://doi.org/10.5281/zenodo.19357385","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.19357385","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"doi:10.5281/zenodo.19357384","doi":"https://doi.org/10.5281/zenodo.19357384","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.19357384","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article-journal"},"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"display_name":"Affordable and clean energy","score":0.884316086769104,"id":"https://metadata.un.org/sdg/7"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Low-power":[0],"arithmetic":[1],"circuits":[2],"play":[3],"a":[4],"crucial":[5],"role":[6],"in":[7,125,166],"modern":[8],"digital":[9,168],"signal":[10,172],"processing,":[11],"embedded":[12,178],"systems,":[13],"and":[14,33,48,81,89,105,113,120,132,156,176],"portable":[15,174],"electronic":[16],"devices.":[17],"Among":[18],"these":[19],"circuits,":[20],"multipliers":[21],"are":[22],"fundamental":[23],"components":[24],"that":[25,138],"significantly":[26],"influence":[27],"the":[28,46,59,98,139,160],"overall":[29],"power":[30,63,103,128,145],"consumption,":[31,129],"speed,":[32],"area":[34,133,157],"of":[35,50,61,127],"Very":[36],"Large":[37],"Scale":[38],"Integration":[39],"(VLSI)":[40],"systems.":[41],"This":[42],"work":[43],"focuses":[44],"on":[45],"design":[47,96,110,118,161],"analysis":[49],"an":[51],"8-bit":[52,141],"multiplier":[53,72,142,150],"for":[54,164],"low-power":[55,95,167],"VLSI":[56,117],"applications":[57],"with":[58],"objective":[60],"reducing":[62],"dissipation":[64],"while":[65,152],"maintaining":[66,153],"efficient":[67,82],"computational":[68],"performance.":[69,158],"The":[70,109],"proposed":[71,140],"architecture":[73],"is":[74,111,123,162],"designed":[75],"using":[76,115],"optimized":[77],"partial":[78],"product":[79],"generation":[80],"addition":[83],"techniques":[84],"to":[85,148],"minimize":[86],"switching":[87],"activity":[88],"hardware":[90],"complexity.":[91],"By":[92],"employing":[93],"suitable":[94,163],"strategies,":[97],"circuit":[99],"achieves":[100],"reduced":[101],"dynamic":[102],"consumption":[104],"improved":[106],"operational":[107],"efficiency.":[108],"implemented":[112],"simulated":[114],"standard":[116],"tools,":[119],"its":[121],"performance":[122],"evaluated":[124],"terms":[126],"propagation":[130],"delay,":[131],"utilization":[134],"Simulation":[135],"results":[136],"demonstrate":[137],"provides":[143],"better":[144],"efficiency":[146],"compared":[147],"conventional":[149],"architectures":[151],"acceptable":[154],"speed":[155],"Therefore,":[159],"integration":[165],"systems":[169],"such":[170],"as":[171],"processors,":[173],"devices,":[175],"energy-efficient":[177],"applications.":[179]},"counts_by_year":[],"updated_date":"2026-10-17T09:40:24.721904","created_date":"2026-04-02T00:00:00"}
