{"id":"https://openalex.org/W7140534603","doi":"https://doi.org/10.1145/3804449","title":"Pipelined FPGA Implementation of a Differential Evolution Engine for Optimization of Scientific Models","display_name":"Pipelined FPGA Implementation of a Differential Evolution Engine for Optimization of Scientific Models","publication_year":2026,"publication_date":"2026-03-26","ids":{"openalex":"https://openalex.org/W7140534603","doi":"https://doi.org/10.1145/3804449"},"language":"en","primary_location":{"id":"doi:10.1145/3804449","doi":"https://doi.org/10.1145/3804449","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3804449","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-b","cwts-core","dongbi-c","jufo-1","norway-1","poland-70","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1145/3804449","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083847657","display_name":"Manuel de Castro","orcid":"https://orcid.org/0000-0003-3080-5136","observed_orcids":["https://orcid.org/0000-0003-3080-5136"]},"institutions":[{"id":"https://openalex.org/I108103353","display_name":"Universidad de Valladolid","ror":"https://ror.org/01fvbaw18","country_code":"ES","type":"education","lineage":["https://openalex.org/I108103353"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Manuel de Castro","raw_affiliation_strings":["Dpto. de Inform\u00e1tica, Universidad de Valladolid, Valladolid, Spain"],"raw_orcid":"https://orcid.org/0000-0003-3080-5136","affiliations":[{"raw_affiliation_string":"Dpto. de Inform\u00e1tica, Universidad de Valladolid, Valladolid, Spain","institution_ids":["https://openalex.org/I108103353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085443064","display_name":"Roberto Osorio","orcid":"https://orcid.org/0000-0001-8768-2240","observed_orcids":["https://orcid.org/0000-0001-8768-2240"]},"institutions":[{"id":"https://openalex.org/I11019714","display_name":"Universidade da Coru\u00f1a","ror":"https://ror.org/01qckj285","country_code":"ES","type":"education","lineage":["https://openalex.org/I11019714"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Roberto R. Osorio","raw_affiliation_strings":["CITIC, Computer Architecture Group, Universidade da Coru\u00f1a, A Coru\u00f1a, Spain"],"raw_orcid":"https://orcid.org/0000-0001-8768-2240","affiliations":[{"raw_affiliation_string":"CITIC, Computer Architecture Group, Universidade da Coru\u00f1a, A Coru\u00f1a, Spain","institution_ids":["https://openalex.org/I11019714"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072874402","display_name":"Yuri Torres","orcid":"https://orcid.org/0000-0002-3037-3567","observed_orcids":["https://orcid.org/0000-0002-3037-3567"]},"institutions":[{"id":"https://openalex.org/I108103353","display_name":"Universidad de Valladolid","ror":"https://ror.org/01fvbaw18","country_code":"ES","type":"education","lineage":["https://openalex.org/I108103353"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Yuri Torres","raw_affiliation_strings":["Dpto. de Inform\u00e1tica, Universidad de Valladolid, Valladolid, Spain"],"raw_orcid":"https://orcid.org/0000-0002-3037-3567","affiliations":[{"raw_affiliation_string":"Dpto. de Inform\u00e1tica, Universidad de Valladolid, Valladolid, Spain","institution_ids":["https://openalex.org/I108103353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043394187","display_name":"Diego R. Llanos","orcid":"https://orcid.org/0000-0001-6240-9109","observed_orcids":["https://orcid.org/0000-0001-6240-9109"]},"institutions":[{"id":"https://openalex.org/I108103353","display_name":"Universidad de Valladolid","ror":"https://ror.org/01fvbaw18","country_code":"ES","type":"education","lineage":["https://openalex.org/I108103353"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Diego R. Llanos","raw_affiliation_strings":["Dpto. de Inform\u00e1tica, Universidad de Valladolid, Valladolid, Spain"],"raw_orcid":"https://orcid.org/0000-0001-6240-9109","affiliations":[{"raw_affiliation_string":"Dpto. de Inform\u00e1tica, Universidad de Valladolid, Valladolid, Spain","institution_ids":["https://openalex.org/I108103353"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20537614,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"19","issue":"2","first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9570000171661377,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9570000171661377,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.013899999670684338,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.006500000134110451,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/differential-evolution","display_name":"differential evolution","score":0.9589999914169312},{"id":"https://openalex.org/keywords/fpga-acceleration","display_name":"FPGA acceleration","score":0.6389999985694885},{"id":"https://openalex.org/keywords/pipelined-architecture","display_name":"pipelined architecture","score":0.8880000114440918},{"id":"https://openalex.org/keywords/adaptive-numerical-integration","display_name":"adaptive numerical integration","score":0.7839999794960022},{"id":"https://openalex.org/keywords/hodgkin-huxley-model","display_name":"Hodgkin-Huxley model","score":0.9350000023841858},{"id":"https://openalex.org/keywords/arabidopsis-thaliana","display_name":"Arabidopsis thaliana","score":1.0},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.800000011920929},{"id":"https://openalex.org/keywords/floating-point-arithmetic","display_name":"floating-point arithmetic","score":0.8270000219345093}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8672999739646912},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6431000232696533},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6347000002861023},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5425999760627747},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5328999757766724},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4717000126838684},{"id":"https://openalex.org/C139807058","wikidata":"https://www.wikidata.org/wiki/Q352374","display_name":"Adaptation (eye)","level":2,"score":0.4505999982357025},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.42419999837875366},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.412200003862381},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.39570000767707825},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38909998536109924},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3873000144958496},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35989999771118164},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.3497999906539917},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.3456999957561493},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.34310001134872437},{"id":"https://openalex.org/C74750220","wikidata":"https://www.wikidata.org/wiki/Q2662197","display_name":"Differential evolution","level":2,"score":0.32899999618530273},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.32350000739097595},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.3018999993801117},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.296999990940094},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.29190000891685486},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2892000079154968},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.2888999879360199},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.2775999903678894},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.2759999930858612},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.2639000117778778},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.2574000060558319}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3804449","doi":"https://doi.org/10.1145/3804449","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3804449","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-b","cwts-core","dongbi-c","jufo-1","norway-1","poland-70","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3804449","doi":"https://doi.org/10.1145/3804449","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3804449","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-b","cwts-core","dongbi-c","jufo-1","norway-1","poland-70","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7638006806373596}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1595159159","https://openalex.org/W1985940938","https://openalex.org/W2005666336","https://openalex.org/W2009939776","https://openalex.org/W2029378989","https://openalex.org/W2038456806","https://openalex.org/W2039858776","https://openalex.org/W2048792111","https://openalex.org/W2066019264","https://openalex.org/W2081745314","https://openalex.org/W2084154180","https://openalex.org/W2559381759","https://openalex.org/W2901554125","https://openalex.org/W4253669045","https://openalex.org/W4310551536","https://openalex.org/W4311839720","https://openalex.org/W4386563438","https://openalex.org/W4387639169","https://openalex.org/W4391164386","https://openalex.org/W4409409738"],"related_works":[],"abstract_inverted_index":{"Custom":[0],"computing":[1],"machines":[2],"implemented":[3],"on":[4],"FPGAs":[5,58,180],"have":[6],"emerged":[7],"as":[8,181],"a":[9,30,72,182],"powerful":[10],"solution":[11],"for":[12,20,62,79,95,113,185,196],"tackling":[13],"computationally":[14],"intensive":[15],"tasks,":[16],"leveraging":[17],"their":[18,65],"capacity":[19],"deep":[21],"pipelining":[22],"and":[23,74,91,98,117,134,138,144,169,193],"parallel":[24],"memory":[25],"access.":[26],"Differential":[27],"Evolution":[28],"(DE),":[29],"robust":[31],"optimization":[32,89,165],"algorithm,":[33],"combined":[34],"with":[35,132],"adaptive":[36,129],"numerical":[37,130],"integration":[38,99],"methods,":[39],"is":[40,83,92,208],"widely":[41],"used":[42],"to":[43,85,203],"optimize":[44],"parameter":[45],"values":[46],"in":[47],"diverse":[48],"scientific":[49,161,187],"models.":[50],"These":[51],"tasks":[52],"involve":[53],"extensive":[54],"floating-point":[55],"computations,":[56],"making":[57],"an":[59],"ideal":[60],"platform":[61,184],"efficiently":[63],"accelerating":[64],"execution.":[66],"In":[67],"this":[68,206],"work,":[69],"we":[70,105],"present":[71],"flexible":[73],"scalable":[75],"FPGA":[76],"architecture":[77,82,127],"optimized":[78],"DE.":[80],"This":[81],"tailored":[84],"solve":[86],"complex,":[87],"resource-intensive":[88],"problems":[90],"easily":[93],"customizable":[94],"various":[96],"models":[97],"methods.":[100],"To":[101],"demonstrate":[102],"its":[103],"efficacy,":[104],"evaluate":[106],"two":[107],"case":[108],"studies:":[109],"The":[110,174,200],"Hodgkin\u2013Huxley":[111],"model":[112,121],"neuron":[114],"action":[115],"potentials":[116],"the":[118,177],"Circadian":[119],"clock":[120],"of":[122,166,171,179],"Arabidopsis":[123],"thaliana":[124],".":[125,213],"Our":[126,152],"integrates":[128],"methods":[131],"DE":[133],"achieves":[135],"significant":[136],"performance":[137],"energy":[139,191],"efficiency":[140,192],"gains":[141],"over":[142],"CPU":[143],"GPU":[145],"implementations":[146],"while":[147],"maintaining":[148],"versatility":[149],"across":[150,159],"applications.":[151],"architecture\u2019s":[153],"modular":[154],"design":[155],"enables":[156],"seamless":[157],"adaptation":[158],"different":[160],"contexts,":[162],"enabling":[163],"further":[164],"resource":[167],"utilization":[168],"expansion":[170],"application":[172],"domains.":[173],"results":[175],"underline":[176],"potential":[178],"superior":[183],"large-scale":[186],"computation,":[188],"offering":[189],"unmatched":[190],"computational":[194],"throughput":[195],"highly":[197],"demanding":[198],"tasks.":[199],"code":[201],"developed":[202],"carry":[204],"out":[205],"work":[207],"publicly":[209],"available":[210],"at":[211],"https://github.com/mdccUVa/de-fpga":[212]},"counts_by_year":[],"updated_date":"2026-10-14T16:39:01.820549","created_date":"2026-03-27T00:00:00"}
