{"id":"https://openalex.org/W7128805249","doi":"https://doi.org/10.1109/iceca66444.2025.11383489","title":"A Comprehensive Survey of Clock-Gating Techniques for Low-Power VLSI Design","display_name":"A Comprehensive Survey of Clock-Gating Techniques for Low-Power VLSI Design","publication_year":2025,"publication_date":"2025-11-05","ids":{"openalex":"https://openalex.org/W7128805249","doi":"https://doi.org/10.1109/iceca66444.2025.11383489"},"language":"en","primary_location":{"id":"doi:10.1109/iceca66444.2025.11383489","doi":"https://doi.org/10.1109/iceca66444.2025.11383489","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceca66444.2025.11383489","pdf_url":null,"source":{"id":"https://openalex.org/S4363607835","display_name":"International Conference on Electronics, Communication and Aerospace Technology (ICECA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 9th International Conference on Electronics, Communication and Aerospace Technology (ICECA)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115632296","display_name":"D. V. N. Bharathi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4400009046","display_name":"SRKR Engineering College","ror":"https://ror.org/038qac964","country_code":"IN","type":"education","lineage":["https://openalex.org/I4400009046"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"D.V.N.Bharathi","raw_affiliation_strings":["S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India","institution_ids":["https://openalex.org/I4400009046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067044065","display_name":"K. Bala Sindhuri","orcid":"https://orcid.org/0000-0001-7892-2062","observed_orcids":["https://orcid.org/0000-0001-7892-2062"]},"institutions":[{"id":"https://openalex.org/I4400009046","display_name":"SRKR Engineering College","ror":"https://ror.org/038qac964","country_code":"IN","type":"education","lineage":["https://openalex.org/I4400009046"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bala Sindhuri Kandula","raw_affiliation_strings":["S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India","institution_ids":["https://openalex.org/I4400009046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125991654","display_name":"Vignesh Naga Trinadh Kalepu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4400009046","display_name":"SRKR Engineering College","ror":"https://ror.org/038qac964","country_code":"IN","type":"education","lineage":["https://openalex.org/I4400009046"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vignesh Naga Trinadh Kalepu","raw_affiliation_strings":["S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India","institution_ids":["https://openalex.org/I4400009046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125979928","display_name":"Yashwanth Korada","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4400009046","display_name":"SRKR Engineering College","ror":"https://ror.org/038qac964","country_code":"IN","type":"education","lineage":["https://openalex.org/I4400009046"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Yashwanth Korada","raw_affiliation_strings":["S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India","institution_ids":["https://openalex.org/I4400009046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125921275","display_name":"Tejaswi Kammila","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4400009046","display_name":"SRKR Engineering College","ror":"https://ror.org/038qac964","country_code":"IN","type":"education","lineage":["https://openalex.org/I4400009046"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tejaswi Kammila","raw_affiliation_strings":["S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India","institution_ids":["https://openalex.org/I4400009046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125956620","display_name":"Manikanta Santhosh Kanchi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4400009046","display_name":"SRKR Engineering College","ror":"https://ror.org/038qac964","country_code":"IN","type":"education","lineage":["https://openalex.org/I4400009046"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Manikanta Santhosh Kanchi","raw_affiliation_strings":["S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"S.R.K.R Engineering College(A),Center of Excellence in VLSI Design,Department of E.C.E,Bhimavaram,India","institution_ids":["https://openalex.org/I4400009046"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4400009046"],"apc_list":null,"apc_paid":null,"fwci":8.86,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.98610851,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"398","last_page":"405"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0010999999940395355,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"clock gating","score":0.9990000128746033},{"id":"https://openalex.org/keywords/low-power-vlsi-design","display_name":"low-power VLSI design","score":0.925000011920929},{"id":"https://openalex.org/keywords/dynamic-power-reduction","display_name":"dynamic power reduction","score":0.9950000047683716},{"id":"https://openalex.org/keywords/area-overhead","display_name":"area overhead","score":0.7070000171661377},{"id":"https://openalex.org/keywords/power-performance-area-tradeoff","display_name":"power-performance-area tradeoff","score":0.7599999904632568}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8314999938011169},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.722599983215332},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6413999795913696},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5685999989509583},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4814999997615814},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.4797999858856201},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.446399986743927},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4359000027179718},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4291999936103821},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.40869998931884766},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4027999937534332},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.39579999446868896},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3790999948978424},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.3605000078678131},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.357699990272522},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.3522000014781952},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.34779998660087585},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.3418999910354614},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3398999869823456},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33799999952316284},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.33550000190734863},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.335099995136261},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.3327000141143799},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.32659998536109924},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31940001249313354},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.3179999887943268},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3084000051021576},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.29429998993873596},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2939999997615814},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2827000021934509},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.2777000069618225},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2773999869823456},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.2754000127315521},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.2696000039577484},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2563000023365021}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceca66444.2025.11383489","doi":"https://doi.org/10.1109/iceca66444.2025.11383489","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceca66444.2025.11383489","pdf_url":null,"source":{"id":"https://openalex.org/S4363607835","display_name":"International Conference on Electronics, Communication and Aerospace Technology (ICECA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 9th International Conference on Electronics, Communication and Aerospace Technology (ICECA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6773999929428101}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1510566755","https://openalex.org/W2073623973","https://openalex.org/W2080075495","https://openalex.org/W2081344774","https://openalex.org/W2098750459","https://openalex.org/W2111128915","https://openalex.org/W2114132980","https://openalex.org/W2119205794","https://openalex.org/W2123714662","https://openalex.org/W2137310043","https://openalex.org/W2531311033","https://openalex.org/W2783928308","https://openalex.org/W2902459906","https://openalex.org/W2907573123","https://openalex.org/W2943713805","https://openalex.org/W2996859601","https://openalex.org/W3135140818","https://openalex.org/W3168434913","https://openalex.org/W4407832320","https://openalex.org/W4409103638"],"related_works":["https://openalex.org/W4412624349","https://openalex.org/W4399686107","https://openalex.org/W7139101047","https://openalex.org/W4386948726","https://openalex.org/W3135140818","https://openalex.org/W3166128015","https://openalex.org/W4285549383","https://openalex.org/W7128682977","https://openalex.org/W7218135112","https://openalex.org/W4285171868"],"abstract_inverted_index":{"Power":[0],"consumption":[1],"from":[2,57],"the":[3,139,144],"clock":[4,54,114],"network,":[5],"which":[6],"can":[7],"account":[8],"for":[9,29,127],"15-45%":[10],"of":[11,52,97,118],"total":[12],"power":[13,109],"in":[14,151],"modern":[15,152],"VLSI":[16,153],"circuits,":[17],"presents":[18],"a":[19,26,46,124,131],"critical":[20],"design":[21,86],"challenge.":[22],"Clock":[23,71,103],"gating":[24,55],"is":[25,76,121,137],"fundamental":[27],"technique":[28],"mitigating":[30],"this":[31,119],"issue":[32],"by":[33,111],"selectively":[34],"disabling":[35],"idle":[36],"circuit":[37],"segments":[38],"to":[39,63,122,142],"reduce":[40],"dynamic":[41,108],"power.":[42],"This":[43],"paper":[44],"provides":[45],"comprehensive":[47],"survey":[48,120],"and":[49,60,69,85,149,154],"comparative":[50],"analysis":[51],"various":[53],"methodologies,":[56],"simple":[58],"gate-based":[59],"latch-based":[61],"approaches":[62],"advanced":[64,99],"data-aware":[65],"schemes":[66],"like":[67,101],"Data-Driven(DDCG)":[68],"Look-Ahead":[70,102],"Gating":[72,104],"(LACG).":[73],"Each":[74],"method":[75],"evaluated":[77],"based":[78],"on":[79],"its":[80],"power-saving":[81],"effectiveness,":[82],"area":[83,150],"overhead,":[84],"complexity.":[87],"Key":[88],"findings":[89],"reveal":[90],"that":[91,130],"while":[92],"simpler":[93],"methods":[94],"offer":[95],"ease":[96],"implementation,":[98],"techniques":[100,136],"(LACG)":[105],"provide":[106,123],"superior":[107],"reduction":[110],"intelligently":[112],"anticipating":[113],"activity.":[115],"The":[116],"significance":[117],"clear":[125],"framework":[126],"designers,":[128],"concluding":[129],"hybrid":[132],"strategy":[133],"combining":[134],"multiple":[135],"often":[138],"optimal":[140],"approach":[141],"balance":[143],"trade-offs":[145],"between":[146],"power,":[147],"performance,":[148],"FPGA":[155],"systems.":[156]},"counts_by_year":[{"year":2026,"cited_by_count":5}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2026-02-14T00:00:00"}