{"id":"https://openalex.org/W7100925447","doi":null,"title":"A systolic FFT architecture for real time FPGA systems,\u201d High Performance Embedded Computing Conference (HPEC04","display_name":"A systolic FFT architecture for real time FPGA systems,\u201d High Performance Embedded Computing Conference (HPEC04","publication_year":null,"publication_date":null,"ids":{"openalex":"https://openalex.org/W7100925447"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.121.6651","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.121.6651","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ll.mit.edu/hpec/agendas/proc04/abstracts/jackson_preston.pdf","raw_type":"text"},"parent_works":[],"lineage":["https://openalex.org/W7100925447"],"child_works_count":0,"type":"conference-abstract","is_traditional":false,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006683345","display_name":"Preston A. Jackson","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Preston A. Jackson","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005140361","display_name":"Cy P. Chan","orcid":"https://orcid.org/0000-0001-6881-827X","observed_orcids":["https://orcid.org/0000-0001-6881-827X"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Cy P. Chan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062739163","display_name":"Jonathan E. Scalera","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jonathan E. Scalera","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012582861","display_name":"Charles M. Rader","orcid":"https://orcid.org/0000-0002-7908-4053","observed_orcids":["https://orcid.org/0000-0002-7908-4053"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Charles M. Rader","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5109862832","display_name":"M. Vai","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Michael Vai","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9735999703407288,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9735999703407288,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.01889999955892563,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.00139999995008111,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.7289999723434448},{"id":"https://openalex.org/keywords/parallel-fft","display_name":"parallel FFT","score":0.5019999742507935},{"id":"https://openalex.org/keywords/high-throughput","display_name":"high throughput","score":0.5799999833106995},{"id":"https://openalex.org/keywords/numerical-accuracy","display_name":"numerical accuracy","score":0.9909999966621399},{"id":"https://openalex.org/keywords/xilinx-virtex-ii","display_name":"Xilinx Virtex-II","score":0.7170000076293945},{"id":"https://openalex.org/keywords/embedded-computing","display_name":"embedded computing","score":0.35600000619888306},{"id":"https://openalex.org/keywords/digital-signal-processing-hardware","display_name":"digital signal processing hardware","score":0.515999972820282}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7300000190734863},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7228999733924866},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6855000257492065},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6183000206947327},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5378000140190125},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.46209999918937683},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4027999937534332},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3977000117301941},{"id":"https://openalex.org/C2985918086","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel architecture","level":3,"score":0.37470000982284546},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.33489999175071716},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.329800009727478},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.32120001316070557},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.30959999561309814},{"id":"https://openalex.org/C28472234","wikidata":"https://www.wikidata.org/wiki/Q213666","display_name":"Real-time operating system","level":2,"score":0.29440000653266907},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.2806999981403351},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.27630001306533813},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.26980000734329224},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.2556000053882599},{"id":"https://openalex.org/C19012869","wikidata":"https://www.wikidata.org/wiki/Q578372","display_name":"Response time","level":2,"score":0.2502000033855438}],"mesh":[],"locations_count":3,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.121.6651","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.121.6651","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ll.mit.edu/hpec/agendas/proc04/abstracts/jackson_preston.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.211.4835","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.211.4835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://people.csail.mit.edu/cychan/papers/systolicfft-abstract.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.476.2629","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.476.2629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.dtic.mil/dtic/tr/fulltext/u2/a433002.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1600409781","https://openalex.org/W2373604608","https://openalex.org/W2054380271","https://openalex.org/W2142364191","https://openalex.org/W1975985301","https://openalex.org/W4232570329","https://openalex.org/W2063910507","https://openalex.org/W1491187403","https://openalex.org/W2542512280","https://openalex.org/W2321570951"],"abstract_inverted_index":{"MIT":[0],"Lincoln":[1],"Laboratory":[2],"has":[3,84],"recently":[4],"developed":[5],"a":[6,16,52],"new":[7],"systolic":[8],"FFT":[9],"architecture":[10,14,71],"for":[11],"FPGAs.":[12],"This":[13],"utilizes":[15],"parallel":[17],"design":[18],"to":[19],"provide":[20],"high":[21,62],"throughput":[22],"and":[23,41],"excellent":[24],"numerical":[25],"accuracy.":[26],"Using":[27],"this":[28,70],"design,":[29],"an":[30],"8192-point":[31],"real-time":[32],"FFT,":[33,61],"operating":[34],"at":[35],"1.2":[36],"billion":[37],"samples":[38],"per":[39],"second":[40],"performing":[42],"78":[43],"Gops":[44],"with":[45,69],"70":[46],"dB":[47],"of":[48,75],"accuracy,":[49],"fits":[50],"on":[51],"single":[53],"Xilinx":[54],"Virtex":[55],"II":[56],"8000.":[57],"Keywords:":[58],"FPGA,":[59],"DFT,":[60],"performance,":[63],"parallel,":[64],"systolic,":[65],"correlation.":[66],"serial":[67],"data":[68,82],"would":[72],"leave":[73],"much":[74],"the":[76,80],"circuitry":[77],"idle":[78],"until":[79],"input":[81],"sequence":[83],"streamed":[85],"in.":[86],"1.":[87]},"counts_by_year":[],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2025-10-27T00:00:00"}