{"id":"https://openalex.org/W7097346844","doi":null,"title":"FPGAs vs. CPUs: Trends in Peak Floating-Point","display_name":"FPGAs vs. CPUs: Trends in Peak Floating-Point","publication_year":2008,"publication_date":"2008-02-05","ids":{"openalex":"https://openalex.org/W7097346844"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.61.347","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.61.347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://gaston.sandia.gov/cfupload/ccim_pubs_prod/p171-underwood.pdf","raw_type":"text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Keith Underwood Sandia","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Keith Underwood Sandia","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5673999786376953,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5673999786376953,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.3285999894142151,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.031599998474121094,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.5529999732971191},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"CPU","score":0.7170000076293945},{"id":"https://openalex.org/keywords/moore-s-law","display_name":"Moore's law","score":0.9359999895095825},{"id":"https://openalex.org/keywords/performance-trends","display_name":"performance trends","score":0.8410000205039978},{"id":"https://openalex.org/keywords/multiply-accumulate","display_name":"multiply-accumulate operations","score":0.7680000066757202},{"id":"https://openalex.org/keywords/clock-frequency","display_name":"clock frequency","score":0.5889999866485596},{"id":"https://openalex.org/keywords/processor-architecture","display_name":"processor architecture","score":0.593999981880188},{"id":"https://openalex.org/keywords/hardware-performance-comparison","display_name":"hardware performance comparison","score":0.5799999833106995}],"concepts":[{"id":"https://openalex.org/C2780012671","wikidata":"https://www.wikidata.org/wiki/Q1343870","display_name":"Corollary","level":2,"score":0.5662000179290771},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5356000065803528},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5217000246047974},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4641999900341034},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.3578000068664551},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3280999958515167},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3278000056743622},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3018999993801117},{"id":"https://openalex.org/C187123476","wikidata":"https://www.wikidata.org/wiki/Q1197550","display_name":"Computer performance","level":2,"score":0.29350000619888306},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2858000099658966},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.2838999927043915},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2827000021934509},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.27070000767707825},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.26339998841285706},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.2563999891281128},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.25589999556541443},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.2524000108242035}],"mesh":[],"locations_count":1,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.61.347","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.61.347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://gaston.sandia.gov/cfupload/ccim_pubs_prod/p171-underwood.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W7097585810","https://openalex.org/W2115002670","https://openalex.org/W7100860104","https://openalex.org/W2092633783","https://openalex.org/W1976535749","https://openalex.org/W2085612442","https://openalex.org/W7099659703","https://openalex.org/W2770165898","https://openalex.org/W2671640592","https://openalex.org/W2171768221"],"abstract_inverted_index":{"Moore's":[0,31,56],"Law":[1,32,57],"states":[2,33],"that":[3,34,89],"the":[4,53,59,75],"number":[5],"of":[6,30,44,55,63,78],"transistors":[7],"on":[8,21,24,58],"a":[9,42,79,103],"device":[10],"doubles":[11],"every":[12,47],"two":[13],"years;":[14],"however,":[15],"it":[16],"is":[17,88,94],"often":[18],"(mis)quoted":[19],"based":[20],"its":[22],"impact":[23,54],"CPU":[25,45],"performance.":[26],"This":[27,50],"important":[28,86],"corollary":[29],"improved":[35,39],"clock":[36],"frequency":[37],"plus":[38],"architecture":[40],"yields":[41],"doubling":[43],"performance":[46,62,76,93,101],"18":[48],"months.":[49],"paper":[51],"examines":[52],"peak":[60,90,99],"floating-point":[61,92,100],"FPGAs.":[64],"Performance":[65],"trends":[66],"for":[67,102],"individual":[68],"operations":[69],"are":[70],"analyzed":[71],"as":[72,74],"well":[73],"trend":[77],"common":[80],"instruction":[81],"mix":[82],"(multiply":[83],"accumulate).":[84],"The":[85],"result":[87],"FPGA":[91],"growing":[95],"significantly":[96],"faster":[97],"than":[98],"CPU.":[104]},"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-27T00:00:00"}
