{"id":"https://openalex.org/W57784367","doi":null,"title":"Fault detection test generation at the register transfer design level","display_name":"Fault detection test generation at the register transfer design level","publication_year":1982,"publication_date":"1982-01-01","ids":{"openalex":"https://openalex.org/W57784367","mag":"57784367"},"language":"en","primary_location":{"id":"mag:57784367","doi":null,"is_oa":false,"landing_page_url":"http://www.osti.gov/scitech/biblio/5000131-fault-detection-test-generation-register-transfer-design-level","pdf_url":null,"source":{"id":"https://openalex.org/S4306402487","display_name":"OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I139351228","host_organization_name":"Office of Scientific and Technical Information","host_organization_lineage":["https://openalex.org/I139351228"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113461995","display_name":"C.H. Chiang","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C.H. Chiang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111867540","display_name":"F.J. Hill","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F.J. Hill","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037437360","display_name":"Amir Mohseni","orcid":"https://orcid.org/0000-0002-2439-2972","observed_orcids":["https://orcid.org/0000-0002-2439-2972"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Amir Mohseni","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0002-2439-2972","affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5055228386","display_name":"D.P. Chen","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D.P. Chen","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.02474794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.0052999998442828655,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fault-detection","display_name":"fault detection","score":0.8519999980926514},{"id":"https://openalex.org/keywords/test-case-generation","display_name":"test case generation","score":0.8759999871253967},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"register transfer level","score":0.7599999904632568},{"id":"https://openalex.org/keywords/vlsi","display_name":"VLSI","score":0.7200000286102295},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.7839999794960022},{"id":"https://openalex.org/keywords/design-automation","display_name":"design automation","score":0.6710000038146973},{"id":"https://openalex.org/keywords/hardware-simulation","display_name":"hardware simulation","score":0.4749999940395355},{"id":"https://openalex.org/keywords/hardware-compilation","display_name":"hardware compilation","score":0.796999990940094}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7315694093704224},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6311530470848083},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5413352251052856},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.5174484848976135},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4870500862598419},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4802599251270294},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.4690932035446167},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45905598998069763},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4409986436367035},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3547593653202057},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3523569703102112},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2453734278678894},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.162973552942276},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14986056089401245},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14047449827194214},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12662452459335327},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.09831541776657104},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:57784367","doi":null,"is_oa":false,"landing_page_url":"http://www.osti.gov/scitech/biblio/5000131-fault-detection-test-generation-register-transfer-design-level","pdf_url":null,"source":{"id":"https://openalex.org/S4306402487","display_name":"OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I139351228","host_organization_name":"Office of Scientific and Technical Information","host_organization_lineage":["https://openalex.org/I139351228"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2107004815","https://openalex.org/W583324347","https://openalex.org/W2168048428","https://openalex.org/W2099876519","https://openalex.org/W2163442697","https://openalex.org/W4238418318","https://openalex.org/W2123024032","https://openalex.org/W2072158017","https://openalex.org/W2197994737","https://openalex.org/W2138223697"],"abstract_inverted_index":{"The":[0,25],"authors":[1],"describe":[2],"the":[3,34,39,58,70],"continuing":[4],"development":[5],"of":[6,10,13,15,19,28,73],"a":[7,29,50,55,74],"program":[8,35,61],"capable":[9],"automatic":[11],"generation":[12,60],"sequences":[14],"inputs":[16],"for":[17],"detection":[18],"faults":[20],"in":[21,38],"VLSI":[22],"digital":[23,30],"networks.":[24],"only":[26],"description":[27,41],"system":[31],"required":[32],"by":[33],"is":[36],"written":[37],"hardware":[40,45,56],"language,":[42],"AHPL":[43],"(a":[44],"programming":[46],"language).":[47],"Together":[48],"with":[49],"function":[51],"level":[52],"simulator":[53],"and":[54],"compiler":[57],"test":[59,66],"called":[62],"SCIRTSS":[63],"(sequential":[64],"circuit":[65],"search":[67],"system)":[68],"form":[69],"front":[71],"end":[72],"design":[75],"automation":[76],"process.":[77],"10":[78],"references.":[79]},"counts_by_year":[],"updated_date":"2025-11-06T04:12:42.849631","created_date":"2016-06-24T00:00:00"}